Design Assistant report for add
Fri Apr 17 15:39:39 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Design Assistant Summary
  3. Design Assistant Settings
  4. Information only Violations
  5. Design Assistant Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; Design Assistant Summary                                                ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status           ; Analyzed - Fri Apr 17 15:39:39 2009 ;
; Revision Name                     ; add                                 ;
; Top-level Entity Name             ; add                                 ;
; Family                            ; MAX II                              ;
; Total Critical Violations         ; 0                                   ;
; Total High Violations             ; 0                                   ;
; Total Medium Violations           ; 0                                   ;
; Total Information only Violations ; 18                                  ;
+-----------------------------------+-------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                                    ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Option                                                                                                                                                                                                                                                                                   ; Setting      ; To ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Design Assistant mode                                                                                                                                                                                                                                                                    ; Post-Fitting ;    ;
; Threshold value for clock net not mapped to clock spines rule                                                                                                                                                                                                                            ; 25           ;    ;
; Minimum number of clock port feed by gated clocks                                                                                                                                                                                                                                        ; 30           ;    ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                           ; 30           ;    ;
; Maximum number of nodes to report                                                                                                                                                                                                                                                        ; 50           ;    ;
; Rule C101: Gated clock should be implemented according to the Altera standard scheme                                                                                                                                                                                                     ; On           ;    ;
; Rule C102: Logic cell should not be used to generate inverted clock                                                                                                                                                                                                                      ; On           ;    ;
; Rule C103: Gated clock is not feeding at least a pre-defined number of clock port to effectively save power                                                                                                                                                                              ; On           ;    ;
; Rule C104: Clock signal source should drive only input clock ports                                                                                                                                                                                                                       ; On           ;    ;
; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.)     ; On           ;    ;
; Rule C106: Clock signal source should not drive registers that are triggered by different clock edges                                                                                                                                                                                    ; On           ;    ;
; Rule R101: Combinational logic used as a reset signal should be synchronized                                                                                                                                                                                                             ; On           ;    ;
; Rule R102: External reset should be synchronized using two cascaded registers                                                                                                                                                                                                            ; On           ;    ;
; Rule R103: External reset should be correctly synchronized                                                                                                                                                                                                                               ; On           ;    ;
; Rule R104: The reset signal that is generated in one clock domain and is used in the other clock domain, should be correctly synchronized                                                                                                                                                ; On           ;    ;
; Rule R105: The reset signal that is generated in one clock domain and is used in the other clock domain, should be synchronized                                                                                                                                                          ; On           ;    ;
; Rule T101: Nodes with more than the specified number of fan-outs                                                                                                                                                                                                                         ; On           ;    ;
; Rule T102: Top nodes with the highest number of fan-outs                                                                                                                                                                                                                                 ; On           ;    ;
; Rule A101: Design should not contain combinational loops                                                                                                                                                                                                                                 ; On           ;    ;
; Rule A102: Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                               ; On           ;    ;
; Rule A103: Design should not contain delay chains                                                                                                                                                                                                                                        ; On           ;    ;
; Rule A104: Design should not contain ripple clock structures                                                                                                                                                                                                                             ; On           ;    ;
; Rule A105: Pulses should not be implemented asynchronously                                                                                                                                                                                                                               ; On           ;    ;
; Rule A106: Multiple pulses should not be generated in design                                                                                                                                                                                                                             ; On           ;    ;
; Rule A107: Design should not contain SR latches                                                                                                                                                                                                                                          ; On           ;    ;
; Rule A108: Design should not contain latches                                                                                                                                                                                                                                             ; On           ;    ;
; Rule A109: Combinational logic should not directly drive write enable signal of asynchronous RAM                                                                                                                                                                                         ; On           ;    ;