{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 14:12:05 2009 " "Info: Processing started: Mon Apr 20 14:12:05 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off add -c add " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off add -c add" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file add.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add-arch " "Info: Found design unit 1: add-arch" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add " "Info: Found entity 1: add" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 11 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "add " "Info: Elaborating entity \"add\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "c\[0\] VCC " "Warning (13410): Pin \"c\[0\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 15 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[0\] GND " "Warning (13410): Pin \"en\[0\]\" is stuck at GND" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[1\] VCC " "Warning (13410): Pin \"en\[1\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[2\] VCC " "Warning (13410): Pin \"en\[2\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[3\] VCC " "Warning (13410): Pin \"en\[3\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[4\] VCC " "Warning (13410): Pin \"en\[4\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[5\] VCC " "Warning (13410): Pin \"en\[5\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[6\] VCC " "Warning (13410): Pin \"en\[6\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "en\[7\] VCC " "Warning (13410): Pin \"en\[7\]\" is stuck at VCC" {  } { { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 16 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "34 " "Info: Implemented 34 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Peak virtual memory: 171 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 20 14:12:09 2009 " "Info: Processing ended: Mon Apr 20 14:12:09 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}