{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 14:12:19 2009 " "Info: Processing started: Mon Apr 20 14:12:19 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off add -c add " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add -c add" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] c\[6\] 12.034 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"c\[6\]\" is 12.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[0\] 1 PIN PIN_71 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 3; PIN Node = 'a\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.200 ns) 4.832 ns Add0~309 2 COMB LC_X13_Y7_N8 2 " "Info: 2: + IC(3.500 ns) + CELL(0.200 ns) = 4.832 ns; Loc. = LC_X13_Y7_N8; Fanout = 2; COMB Node = 'Add0~309'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { a[0] Add0~309 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(0.200 ns) 5.772 ns Add0~310 3 COMB LC_X13_Y7_N4 7 " "Info: 3: + IC(0.740 ns) + CELL(0.200 ns) = 5.772 ns; Loc. = LC_X13_Y7_N4; Fanout = 7; COMB Node = 'Add0~310'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.940 ns" { Add0~309 Add0~310 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.511 ns) 7.118 ns Mux1~3 4 COMB LC_X13_Y7_N6 1 " "Info: 4: + IC(0.835 ns) + CELL(0.511 ns) = 7.118 ns; Loc. = LC_X13_Y7_N6; Fanout = 1; COMB Node = 'Mux1~3'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.346 ns" { Add0~310 Mux1~3 } "NODE_NAME" } } { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.594 ns) + CELL(2.322 ns) 12.034 ns c\[6\] 5 PIN PIN_108 0 " "Info: 5: + IC(2.594 ns) + CELL(2.322 ns) = 12.034 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'c\[6\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { Mux1~3 c[6] } "NODE_NAME" } } { "add.vhd" "" { Text "C:/altera/80/quartus/vhdl/basicexperiment/adder/add.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.365 ns ( 36.27 % ) " "Info: Total cell delay = 4.365 ns ( 36.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.669 ns ( 63.73 % ) " "Info: Total interconnect delay = 7.669 ns ( 63.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.034 ns" { a[0] Add0~309 Add0~310 Mux1~3 c[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.034 ns" { a[0] {} a[0]~combout {} Add0~309 {} Add0~310 {} Mux1~3 {} c[6] {} } { 0.000ns 0.000ns 3.500ns 0.740ns 0.835ns 2.594ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.511ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "121 " "Info: Peak virtual memory: 121 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 20 14:12:20 2009 " "Info: Processing ended: Mon Apr 20 14:12:20 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}