?? cmp.tan.rpt
字號:
Timing Analyzer report for cmp
Sat Feb 18 15:06:41 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.745 ns ; a[0] ; c[2] ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270T144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 10.745 ns ; a[0] ; c[2] ;
; N/A ; None ; 10.718 ns ; b[1] ; c[2] ;
; N/A ; None ; 10.697 ns ; a[1] ; c[2] ;
; N/A ; None ; 10.568 ns ; a[0] ; c[7] ;
; N/A ; None ; 10.541 ns ; b[1] ; c[7] ;
; N/A ; None ; 10.520 ns ; a[1] ; c[7] ;
; N/A ; None ; 10.371 ns ; b[0] ; c[2] ;
; N/A ; None ; 10.194 ns ; b[0] ; c[7] ;
; N/A ; None ; 10.182 ns ; a[2] ; c[2] ;
; N/A ; None ; 10.153 ns ; a[0] ; c[3] ;
; N/A ; None ; 10.149 ns ; a[0] ; c[4] ;
; N/A ; None ; 10.126 ns ; b[1] ; c[3] ;
; N/A ; None ; 10.122 ns ; b[1] ; c[4] ;
; N/A ; None ; 10.105 ns ; a[1] ; c[3] ;
; N/A ; None ; 10.101 ns ; a[1] ; c[4] ;
; N/A ; None ; 10.005 ns ; a[2] ; c[7] ;
; N/A ; None ; 9.909 ns ; b[2] ; c[2] ;
; N/A ; None ; 9.779 ns ; b[0] ; c[3] ;
; N/A ; None ; 9.775 ns ; b[0] ; c[4] ;
; N/A ; None ; 9.732 ns ; b[2] ; c[7] ;
; N/A ; None ; 9.654 ns ; a[3] ; c[2] ;
; N/A ; None ; 9.590 ns ; a[2] ; c[3] ;
; N/A ; None ; 9.586 ns ; a[2] ; c[4] ;
; N/A ; None ; 9.477 ns ; a[3] ; c[7] ;
; N/A ; None ; 9.392 ns ; b[3] ; c[2] ;
; N/A ; None ; 9.317 ns ; b[2] ; c[3] ;
; N/A ; None ; 9.313 ns ; b[2] ; c[4] ;
; N/A ; None ; 9.215 ns ; b[3] ; c[7] ;
; N/A ; None ; 9.062 ns ; a[3] ; c[3] ;
; N/A ; None ; 9.058 ns ; a[3] ; c[4] ;
; N/A ; None ; 8.800 ns ; b[3] ; c[3] ;
; N/A ; None ; 8.796 ns ; b[3] ; c[4] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Feb 18 15:06:40 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a[0]" to destination pin "c[2]" is 10.745 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'a[0]'
Info: 2: + IC(3.425 ns) + CELL(0.200 ns) = 4.757 ns; Loc. = LC_X13_Y7_N1; Fanout = 1; COMB Node = 'LessThan~349'
Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 5.262 ns; Loc. = LC_X13_Y7_N2; Fanout = 1; COMB Node = 'LessThan~350'
Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 5.767 ns; Loc. = LC_X13_Y7_N3; Fanout = 4; COMB Node = 'LessThan~351'
Info: 5: + IC(2.656 ns) + CELL(2.322 ns) = 10.745 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'c[2]'
Info: Total cell delay = 4.054 ns ( 37.73 % )
Info: Total interconnect delay = 6.691 ns ( 62.27 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Feb 18 15:06:41 2006
Info: Elapsed time: 00:00:02
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