?? mlt.tan.rpt
字號:
Classic Timing Analyzer report for mlt
Fri Apr 17 17:34:29 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.007 ns ; b[0] ; c[1] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270T144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 9.007 ns ; b[0] ; c[1] ;
; N/A ; None ; 8.999 ns ; b[0] ; c[2] ;
; N/A ; None ; 8.853 ns ; a[1] ; c[7] ;
; N/A ; None ; 8.827 ns ; a[1] ; c[1] ;
; N/A ; None ; 8.825 ns ; a[1] ; c[6] ;
; N/A ; None ; 8.822 ns ; a[1] ; c[2] ;
; N/A ; None ; 8.807 ns ; b[1] ; c[1] ;
; N/A ; None ; 8.800 ns ; b[1] ; c[2] ;
; N/A ; None ; 8.793 ns ; a[0] ; c[3] ;
; N/A ; None ; 8.762 ns ; b[0] ; c[7] ;
; N/A ; None ; 8.734 ns ; b[0] ; c[6] ;
; N/A ; None ; 8.689 ns ; b[0] ; c[5] ;
; N/A ; None ; 8.673 ns ; a[0] ; c[1] ;
; N/A ; None ; 8.665 ns ; a[0] ; c[2] ;
; N/A ; None ; 8.563 ns ; a[0] ; c[7] ;
; N/A ; None ; 8.523 ns ; a[0] ; c[6] ;
; N/A ; None ; 8.522 ns ; a[0] ; c[5] ;
; N/A ; None ; 8.522 ns ; b[1] ; c[3] ;
; N/A ; None ; 8.496 ns ; a[1] ; c[3] ;
; N/A ; None ; 8.441 ns ; b[1] ; c[4] ;
; N/A ; None ; 8.421 ns ; a[0] ; c[4] ;
; N/A ; None ; 8.414 ns ; b[1] ; c[7] ;
; N/A ; None ; 8.412 ns ; a[1] ; c[5] ;
; N/A ; None ; 8.386 ns ; b[1] ; c[6] ;
; N/A ; None ; 8.385 ns ; b[0] ; c[3] ;
; N/A ; None ; 8.371 ns ; b[0] ; c[4] ;
; N/A ; None ; 8.359 ns ; b[1] ; c[5] ;
; N/A ; None ; 8.211 ns ; a[1] ; c[4] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
Info: Processing started: Fri Apr 17 17:34:29 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "b[0]" to destination pin "c[1]" is 9.007 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_68; Fanout = 7; PIN Node = 'b[0]'
Info: 2: + IC(4.168 ns) + CELL(0.740 ns) = 6.040 ns; Loc. = LC_X11_Y10_N0; Fanout = 1; COMB Node = 'Mux6~3'
Info: 3: + IC(0.645 ns) + CELL(2.322 ns) = 9.007 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'c[1]'
Info: Total cell delay = 4.194 ns ( 46.56 % )
Info: Total interconnect delay = 4.813 ns ( 53.44 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 121 megabytes
Info: Processing ended: Fri Apr 17 17:34:30 2009
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
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