?? mlt.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L52 is Mux~28 at LC_X12_Y3_N8
--operation mode is normal
A1L52 = b[1] & (a[1] # a[0]) # !b[1] & b[0] & a[1];
--A1L62 is Mux~29 at LC_X12_Y3_N0
--operation mode is normal
A1L62 = b[1] & (!a[1] & a[0]) # !b[1] & b[0] & (a[1] # a[0]);
--A1L72 is Mux~30 at LC_X13_Y4_N0
--operation mode is normal
A1L72 = b[0] & (a[0]) # !b[0] & a[1] & b[1] & !a[0];
--A1L82 is Mux~31 at LC_X13_Y4_N8
--operation mode is normal
A1L82 = b[0] & a[0] & (a[1] $ !b[1]) # !b[0] & a[1] & b[1] & !a[0];
--A1L92 is Mux~32 at LC_X15_Y3_N0
--operation mode is normal
A1L92 = a[0] & !a[1] & b[1] & !b[0] # !a[0] & a[1] & !b[1] & b[0];
--A1L03 is Mux~33 at LC_X16_Y2_N6
--operation mode is normal
A1L03 = a[1] & b[1] & (a[0] $ b[0]);
--A1L13 is Mux~34 at LC_X15_Y3_N3
--operation mode is normal
A1L13 = a[0] & !a[1] & !b[1] & b[0] # !a[0] & a[1] & b[1] & !b[0];
--b[1] is b[1] at PIN_67
--operation mode is input
b[1] = INPUT();
--a[1] is a[1] at PIN_69
--operation mode is input
a[1] = INPUT();
--b[0] is b[0] at PIN_68
--operation mode is input
b[0] = INPUT();
--a[0] is a[0] at PIN_71
--operation mode is input
a[0] = INPUT();
--c[0] is c[0] at PIN_120
--operation mode is output
c[0] = OUTPUT(VCC);
--c[1] is c[1] at PIN_119
--operation mode is output
c[1] = OUTPUT(!A1L52);
--c[2] is c[2] at PIN_117
--operation mode is output
c[2] = OUTPUT(A1L62);
--c[3] is c[3] at PIN_114
--operation mode is output
c[3] = OUTPUT(A1L72);
--c[4] is c[4] at PIN_113
--operation mode is output
c[4] = OUTPUT(A1L82);
--c[5] is c[5] at PIN_111
--operation mode is output
c[5] = OUTPUT(A1L92);
--c[6] is c[6] at PIN_108
--operation mode is output
c[6] = OUTPUT(A1L03);
--c[7] is c[7] at PIN_109
--operation mode is output
c[7] = OUTPUT(A1L13);
--en[0] is en[0] at PIN_134
--operation mode is output
en[0] = OUTPUT(GND);
--en[1] is en[1] at PIN_133
--operation mode is output
en[1] = OUTPUT(VCC);
--en[2] is en[2] at PIN_124
--operation mode is output
en[2] = OUTPUT(VCC);
--en[3] is en[3] at PIN_123
--operation mode is output
en[3] = OUTPUT(VCC);
--en[4] is en[4] at PIN_121
--operation mode is output
en[4] = OUTPUT(VCC);
--en[5] is en[5] at PIN_125
--operation mode is output
en[5] = OUTPUT(VCC);
--en[6] is en[6] at PIN_131
--operation mode is output
en[6] = OUTPUT(VCC);
--en[7] is en[7] at PIN_132
--operation mode is output
en[7] = OUTPUT(VCC);
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