+-------------------------------------------------------------------------------+
; th                                                                            ;
+---------------+-------------+-----------+-------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To               ; To Clock ;
+---------------+-------------+-----------+-------+------------------+----------+
; N/A           ; None        ; -1.015 ns ; hold  ; cnum[0]~reg0     ; clk      ;
; N/A           ; None        ; -1.015 ns ; hold  ; cnum[1]~reg0     ; clk      ;
; N/A           ; None        ; -1.015 ns ; hold  ; cnum[4]~reg0     ; clk      ;
; N/A           ; None        ; -1.015 ns ; hold  ; cnum[5]~reg0     ; clk      ;
; N/A           ; None        ; -1.015 ns ; hold  ; cnum[2]~reg0     ; clk      ;
; N/A           ; None        ; -1.015 ns ; hold  ; cnum[3]~reg0     ; clk      ;
; N/A           ; None        ; -1.298 ns ; hold  ; current_state.s2 ; clk      ;
; N/A           ; None        ; -1.403 ns ; hold  ; current_state.s0 ; clk      ;
; N/A           ; None        ; -1.403 ns ; hold  ; current_state.s1 ; clk      ;
; N/A           ; None        ; -1.628 ns ; reset ; current_state.s2 ; clk      ;
; N/A           ; None        ; -1.733 ns ; reset ; current_state.s0 ; clk      ;
; N/A           ; None        ; -1.733 ns ; reset ; current_state.s1 ; clk      ;
+---------------+-------------+-----------+-------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Dec 14 18:04:43 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "cnum[0]~reg0" and destination register "cnum[0]~reg0"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.168 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum[0]~reg0'
            Info: 2: + IC(0.549 ns) + CELL(0.590 ns) = 1.139 ns; Loc. = LC_X20_Y5_N8; Fanout = 1; COMB Node = 'Equal0~56'
            Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.435 ns; Loc. = LC_X20_Y5_N9; Fanout = 9; COMB Node = 'Equal0~57'
            Info: 4: + IC(0.508 ns) + CELL(1.225 ns) = 3.168 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum[0]~reg0'
            Info: Total cell delay = 1.929 ns ( 60.89 % )
            Info: Total interconnect delay = 1.239 ns ( 39.11 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 6.853 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'
                Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum[0]~reg0'
                Info: Total cell delay = 2.180 ns ( 31.81 % )
                Info: Total interconnect delay = 4.673 ns ( 68.19 % )
            Info: - Longest clock path from clock "clk" to source register is 6.853 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'
                Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum[0]~reg0'
                Info: Total cell delay = 2.180 ns ( 31.81 % )
                Info: Total interconnect delay = 4.673 ns ( 68.19 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "current_state.s0" (data pin = "reset", clock pin = "clk") is 1.785 ns
    Info: + Longest pin to register delay is 8.601 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_61; Fanout = 7; PIN Node = 'reset'
        Info: 2: + IC(5.514 ns) + CELL(0.590 ns) = 7.579 ns; Loc. = LC_X21_Y5_N4; Fanout = 3; COMB Node = 'current_state.s0~105'
        Info: 3: + IC(0.713 ns) + CELL(0.309 ns) = 8.601 ns; Loc. = LC_X20_Y5_N0; Fanout = 5; REG Node = 'current_state.s0'
        Info: Total cell delay = 2.374 ns ( 27.60 % )
        Info: Total interconnect delay = 6.227 ns ( 72.40 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 6.853 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N0; Fanout = 5; REG Node = 'current_state.s0'
        Info: Total cell delay = 2.180 ns ( 31.81 % )
        Info: Total interconnect delay = 4.673 ns ( 68.19 % )
Info: tco from clock "clk" to destination pin "cnum[2]" through register "cnum[2]~reg0" is 12.060 ns
    Info: + Longest clock path from clock "clk" to source register is 6.853 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N3; Fanout = 5; REG Node = 'cnum[2]~reg0'
        Info: Total cell delay = 2.180 ns ( 31.81 % )
        Info: Total interconnect delay = 4.673 ns ( 68.19 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.983 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y5_N3; Fanout = 5; REG Node = 'cnum[2]~reg0'
        Info: 2: + IC(2.859 ns) + CELL(2.124 ns) = 4.983 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'cnum[2]'
        Info: Total cell delay = 2.124 ns ( 42.62 % )
        Info: Total interconnect delay = 2.859 ns ( 57.38 % )
Info: th for register "cnum[0]~reg0" (data pin = "hold", clock pin = "clk") is -1.015 ns
    Info: + Longest clock path from clock "clk" to destination register is 6.853 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'
        Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum[0]~reg0'
        Info: Total cell delay = 2.180 ns ( 31.81 % )
        Info: Total interconnect delay = 4.673 ns ( 68.19 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.883 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_60; Fanout = 7; PIN Node = 'hold'
        Info: 2: + IC(5.541 ns) + CELL(0.867 ns) = 7.883 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum[0]~reg0'
        Info: Total cell delay = 2.342 ns ( 29.71 % )
        Info: Total interconnect delay = 5.541 ns ( 70.29 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 110 megabytes of memory during processing
    Info: Processing ended: Sun Dec 14 18:04:44 2008
    Info: Elapsed time: 00:00:01