?? clk.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CLK is
port (clkin:in std_logic;
clkout,clk2: out std_logic);
end CLK;
architecture ctr of CLK is
constant n: integer :=2500;
constant m: integer :=2;
signal q,x:integer range 0 to n;
signal clk,clk1: std_logic;
begin
process(clkin)
begin
if clkin'event and clkin='1' then if x=m and q/=n then x<=0;clk1<=not clk1;
elsif q=n and x/=m then q<=0;clk <=not clk;
elsif q=n and x=m then q<=0;clk <=not clk;x<=0;clk1<=not clk1;
else q<=q+1;x<=x+1;
END IF;
end if;
END PROCESS;
clkout <=clk;
clk2<=clk1;
END CTR;
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