library ieee;
use ieee.std_logic_1164.all;
entity counter3 is
port(clk: in std_logic;
	 reset: in std_logic;
	 hold : in std_logic;
	 led : out std_logic_vector(0 to 2);
	 cnum: buffer integer range 0 to 62);
end counter3;
architecture ctr of counter3 is
type fsm_st is(s0,s1,s2,s3,s4);
signal current_state,next_state:fsm_st;
signal abc: integer range 0 to 62;
begin
process(clk,reset)
begin
if reset='1' then cnum<=0;
elsif rising_edge(clk) then
	if hold='1' then cnum<=cnum;
	elsif cnum=0 then current_state<=next_state;cnum<=abc;
		 else cnum<=cnum-1;
end if;
end if;
end process;
com: process(current_state)
begin
	case current_state is
	 when s0 => abc<=34;next_state<=s1;led<="101";
	 when s1 => abc<=34;next_state<=s2;led<="101";
	 when s2 => abc<=34;next_state<=s3;led<="101";
	 when s3 => abc<=29;next_state<=s4;led<="011";
	 when s4 => abc<=4; next_state<=s0;led<="110";
	
	end case;
	end process;
end ctr;