library ieee;
use ieee.std_logic_1164.all;
entity cctr1 is
port(clk:   in std_logic;
	 reset: in std_logic;
	 hold : in std_logic;
	 leda,ledb,ledc,ledd : out std_logic_vector(0 to 2);
	 cnuma,cnumb,cnumc,cnumd: buffer integer range 0 to 90);
end cctr1;
architecture ctr of cctr1 is
type fsm_st is(s0,s1,s2,s3,s4,s5,s6,s7);
signal next_state:fsm_st;
begin
process(clk,reset)
begin
if reset='1' then cnuma<=0;cnumb<=0;cnumc<=0;cnumd<=0;
			leda<="101";ledb<="101";ledc<="101";ledd<="101";next_state<=s0;
	elsif rising_edge(clk) then	
if hold='1' then 
	cnuma<=cnuma;cnumb<=cnumb;cnumc<=cnumc;cnumd<=cnumd;
elsif (cnuma=0 or cnumb=0 or cnumc=0 or cnumd=0) then 
	case next_state is
	 when s0 => cnuma<=25;cnumb<=30;cnumc<=60;cnumd<=90;
				leda<="011";ledb<="101";ledc<="101";ledd<="101";
				next_state<=s1;
	 when s1 => cnuma<=4;next_state<=s2;leda<="110";cnumb<=cnumb-1;cnumc<=cnumc-1;cnumd<=cnumd-1;
	 when s2 => cnumb<=25;cnuma<=90;
				ledb<="011";leda<="101";ledc<="101";ledd<="101";
				next_state<=s3;
	 when s3 => cnumb<=4;next_state<=s4;ledb<="110";cnuma<=cnuma-1;cnumc<=cnumc-1;cnumd<=cnumd-1;
	 when s4 => cnumc<=25;cnumb<=90;
				ledc<="011";ledb<="101";leda<="101";ledd<="101";
				next_state<=s5;
	 when s5 => cnumc<=4;next_state<=s6;ledc<="110";cnumb<=cnumb-1;cnuma<=cnuma-1;cnumd<=cnumd-1;
	 when s6 => cnumd<=25;cnumc<=90;
				ledd<="011";ledb<="101";ledc<="101";leda<="101";
				next_state<=s7;
	 when s7 => cnumd<=4;ledd<="110";cnuma<=cnuma-1;
				cnumb<=cnumb-1;cnumc<=cnumc-1;next_state<=s0;
	 when others =>next_state<=s0;
	end case;
		 else cnuma<=cnuma-1;cnumb<=cnumb-1;
				cnumc<=cnumc-1;cnumd<=cnumd-1;
end if;
end if;
end process;
end ctr;