?? prev_cmp_second.tan.qmsg
字號:
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off second -c second --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off second -c second --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "xian:inst6\|data1\[7\] " "Warning: Node \"xian:inst6\|data1\[7\]\" is a latch" { } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "xian:inst6\|data1\[6\] " "Warning: Node \"xian:inst6\|data1\[6\]\" is a latch" { } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "xian:inst6\|data1\[5\] " "Warning: Node \"xian:inst6\|data1\[5\]\" is a latch" { } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "xian:inst6\|data1\[4\] " "Warning: Node \"xian:inst6\|data1\[4\]\" is a latch" { } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "xian:inst6\|data1\[3\] " "Warning: Node \"xian:inst6\|data1\[3\]\" is a latch" { } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "xian:inst6\|data1\[2\] " "Warning: Node \"xian:inst6\|data1\[2\]\" is a latch" { } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "xian:inst6\|data1\[1\] " "Warning: Node \"xian:inst6\|data1\[1\]\" is a latch" { } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
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