?? second.fit.qmsg
字號:
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" { } { } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { } { } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.856 ns register register " "Info: Estimated most critical path is register to register delay of 4.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_12:inst5\|QH\[0\] 1 REG LAB_X19_Y10 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y10; Fanout = 6; REG Node = 'cnt_12:inst5\|QH\[0\]'" { } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[0] } "NODE_NAME" } } { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.380 ns) + CELL(0.114 ns) 1.494 ns xian:inst6\|Mux3~63 2 COMB LAB_X19_Y12 1 " "Info: 2: + IC(1.380 ns) + CELL(0.114 ns) = 1.494 ns; Loc. = LAB_X19_Y12; Fanout = 1; COMB Node = 'xian:inst6\|Mux3~63'" { } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { cnt_12:inst5|QH[0] xian:inst6|Mux3~63 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.117 ns) + CELL(0.590 ns) 2.201 ns xian:inst6\|Mux3~64 3 COMB LAB_X19_Y12 1 " "Info: 3: + IC(0.117 ns) + CELL(0.590 ns) = 2.201 ns; Loc. = LAB_X19_Y12; Fanout = 1; COMB Node = 'xian:inst6\|Mux3~64'" { } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.707 ns" { xian:inst6|Mux3~63 xian:inst6|Mux3~64 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 2.855 ns xian:inst6\|Mux3~65 4 COMB LAB_X19_Y12 7 " "Info: 4: + IC(0.212 ns) + CELL(0.442 ns) = 2.855 ns; Loc. = LAB_X19_Y12; Fanout = 7; COMB Node = 'xian:inst6\|Mux3~65'" { } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { xian:inst6|Mux3~64 xian:inst6|Mux3~65 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.757 ns) + CELL(0.590 ns) 4.202 ns xian:inst6\|Mux20~97 5 COMB LAB_X19_Y11 1 " "Info: 5: + IC(0.757 ns) + CELL(0.590 ns) = 4.202 ns; Loc. = LAB_X19_Y11; Fanout = 1; COMB Node = 'xian:inst6\|Mux20~97'" { } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.347 ns" { xian:inst6|Mux3~65 xian:inst6|Mux20~97 } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.442 ns) 4.856 ns xian:inst6\|data1\[6\] 6 REG LAB_X19_Y11 1 " "Info: 6: + IC(0.212 ns) + CELL(0.442 ns) = 4.856 ns; Loc. = LAB_X19_Y11; Fanout = 1; REG Node = 'xian:inst6\|data1\[6\]'" { } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.654 ns" { xian:inst6|Mux20~97 xian:inst6|data1[6] } "NODE_NAME" } } { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 22 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.178 ns ( 44.85 % ) " "Info: Total cell delay = 2.178 ns ( 44.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.678 ns ( 55.15 % ) " "Info: Total interconnect delay = 2.678 ns ( 55.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.856 ns" { cnt_12:inst5|QH[0] xian:inst6|Mux3~63 xian:inst6|Mux3~64 xian:inst6|Mux3~65 xian:inst6|Mux20~97 xian:inst6|data1[6] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_VERY_HIGH_HOLD_REQUIREMENTS_DETECTED" "37 450 " "Warning: 37 (of 450) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." { { "Info" "IFITAPI_FITAPI_INFO_VPR_REGISTERS_WITH_VERY_HIGH_HOLD_REQUIREMENTS" "10 " "Info: Found 10 Registers with very high hold time requirements" { { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_60:inst3\|QH\[3\] " "Info: Node \"cnt_60:inst3\|QH\[3\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_60:inst3\|QH\[3\] " "Info: Registered output is \"cnt_60:inst3\|QH\[3\]\"" { } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux0~47 " "Info: Combinational output is \"xian:inst6\|Mux0~47\"" { } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_12:inst5\|QH\[2\] " "Info: Node \"cnt_12:inst5\|QH\[2\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_12:inst5\|QH\[2\] " "Info: Registered output is \"cnt_12:inst5\|QH\[2\]\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[2\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux1~57 " "Info: Combinational output is \"xian:inst6\|Mux1~57\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[2\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[2\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_12:inst5\|QH\[2\] " "Info: Node \"cnt_12:inst5\|QH\[2\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_12:inst5\|QH\[2\] " "Info: Registered output is \"cnt_12:inst5\|QH\[2\]\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[2\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux1~57 " "Info: Combinational output is \"xian:inst6\|Mux1~57\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[2\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[2\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[2] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_12:inst5\|QH\[3\] " "Info: Node \"cnt_12:inst5\|QH\[3\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_12:inst5\|QH\[3\] " "Info: Registered output is \"cnt_12:inst5\|QH\[3\]\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux0~46 " "Info: Combinational output is \"xian:inst6\|Mux0~46\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_12:inst5\|QH\[3\] " "Info: Node \"cnt_12:inst5\|QH\[3\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_12:inst5\|QH\[3\] " "Info: Registered output is \"cnt_12:inst5\|QH\[3\]\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux0~46 " "Info: Combinational output is \"xian:inst6\|Mux0~46\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment 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"e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux2~44 " "Info: Combinational output is \"xian:inst6\|Mux2~44\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[1\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[1\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_12:inst5\|QH\[1\] " "Info: Node \"cnt_12:inst5\|QH\[1\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_12:inst5\|QH\[1\] " "Info: Registered output is \"cnt_12:inst5\|QH\[1\]\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[1\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux2~44 " "Info: Combinational output is \"xian:inst6\|Mux2~44\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[1\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[1\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_60:inst3\|QH\[3\] " "Info: Node \"cnt_60:inst3\|QH\[3\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_60:inst3\|QH\[3\] " "Info: Registered output is \"cnt_60:inst3\|QH\[3\]\"" { } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux0~47 " "Info: Combinational output is \"xian:inst6\|Mux0~47\"" { } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 16 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_60:inst3\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_60:inst3|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { 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\"cnt_12:inst5\|QH\[1\]\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[1\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux2~44 " "Info: Combinational output is \"xian:inst6\|Mux2~44\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment 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"e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[1] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME_DUAL_OUTPUT" "cnt_12:inst5\|QH\[3\] " "Info: Node \"cnt_12:inst5\|QH\[3\]\" (dual-output)" { { "Info" "IFITAPI_FITAPI_ATOM_REGISTERED_OUTPUT" "cnt_12:inst5\|QH\[3\] " "Info: Registered output is \"cnt_12:inst5\|QH\[3\]\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Registered output is \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_COMBINATORIAL_OUTPUT" "xian:inst6\|Mux0~46 " "Info: Combinational output is \"xian:inst6\|Mux0~46\"" { } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Combinational output is \"%1!s!\"" 0 0 "" 0} } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 17 -1 0 } } { "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/work/quartusii7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt_12:inst5\|QH\[3\]" } } } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } { "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/work/quartusii7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt_12:inst5|QH[3] } "NODE_NAME" } } } 0 0 "Node \"%1!s!\" (dual-output)" 0 0 "" 0} } { } 0 0 "Found %1!d! Registers with very high hold time requirements" 0 0 "" 0} } { } 0 0 "%1!d! (of %2!d!) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Info: Average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "6 X0_Y0 X13_Y14 " "Info: Peak interconnect usage is 6% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
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