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-- Company: 
-- Engineer:
--
-- Create Date:    12:34:46 11/27/08
-- Design Name:    
-- Module Name:    ROM - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ROM is
	 Generic ( data_width: integer := 8;
				  address_width: integer := 4;
			     mem_depth: integer := 32);

    Port ( dir : in std_logic_vector(address_width-1 downto 0);
           dout : out std_logic_vector(data_width-1 downto 0);
			  clk : in std_logic);
end ROM;

architecture Behavioral of ROM is


type rom_typeis array (mem_depth-1 downto0) of STD_LOGIC_VECTOR (data_width-1 downto0);

constant rom: rom_type:=(  "10001010", "11110000", "10101010", "00001111", 
								  	"01010101", "00000000", "11111111", "11001100", 
								   "01010101"); 
begin

	rd: process(clk)
	begin
		if (rising_edge(clk)) then
			data_out<= rom(to_integer(unsigned(dir)));
		end if;
	end process;

end Behavioral;