--altdpram DEVICE_FAMILY=Stratix lpm_hint=RAM_BLOCK_TYPE=AUTO RDCONTROL_ACLR=OFF SUPPRESS_MEMORY_CONVERSION_WARNINGS=ON USE_EAB=ON WIDTH=10 WIDTHAD=4 data inclock outclock outclocken q rdaddress wraddress wren
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
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--  licensors. No other licenses, including any licenses needed under any third
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FUNCTION altsyncram_apb1 (address_a[3..0], address_b[3..0], clock0, clock1, clocken1, data_a[9..0], wren_a)
RETURNS ( q_b[9..0]);

--synthesis_resources = ram_bits (auto) 160 
SUBDESIGN dpram_h2k
( 
	data[9..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	outclocken	:	input;
	q[9..0]	:	output;
	rdaddress[3..0]	:	input;
	wraddress[3..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_apb1;

BEGIN 
	altsyncram1.address_a[] = wraddress[];
	altsyncram1.address_b[] = rdaddress[];
	altsyncram1.clock0 = inclock;
	altsyncram1.clock1 = outclock;
	altsyncram1.clocken1 = outclocken;
	altsyncram1.data_a[] = data[];
	altsyncram1.wren_a = wren;
	q[] = altsyncram1.q_b[];
END;
--VALID FILE