{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 31 13:39:50 2004 " "Info: Processing started: Fri Dec 31 13:39:50 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off uart_regs -c uart_regs --generate_functional_sim_netlist " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off uart_regs -c uart_regs --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../core/myfifo_8.v 1 1 " "Info: Found 1 design units and 1 entities in source file ../core/myfifo_8.v" { { "Info" "ISGN_ENTITY_NAME" "1 myfifo_8 " "Info: Found entity 1: myfifo_8" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/core/myfifo_8.v" "myfifo_8" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/core/myfifo_8.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../core/myfifo_10.v 1 1 " "Info: Found 1 design units and 1 entities in source file ../core/myfifo_10.v" { { "Info" "ISGN_ENTITY_NAME" "1 myfifo_10 " "Info: Found entity 1: myfifo_10" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/core/myfifo_10.v" "myfifo_10" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/core/myfifo_10.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/seriesPort.v 1 1 " "Info: Found 1 design units and 1 entities in source file ../src/seriesPort.v" { { "Info" "ISGN_ENTITY_NAME" "1 series_port " "Info: Found entity 1: series_port" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/seriesPort.v" "series_port" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/seriesPort.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_defines.v 0 0 " "Info: Found 0 design units and 0 entities in source file ../src/uart_defines.v" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_receiver.v 1 1 " "Info: Found 1 design units and 1 entities in source file ../src/uart_receiver.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_receiver " "Info: Found entity 1: uart_receiver" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_receiver.v" "uart_receiver" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_receiver.v" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_CREATED_IMPLICIT_NET" "rf_overrun uart_regs.v(115) " "Warning: Verilog HDL net warning at uart_regs.v(115): created undeclared net rf_overrun" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 115 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_regs.v 1 1 " "Info: Found 1 design units and 1 entities in source file ../src/uart_regs.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_regs " "Info: Found entity 1: uart_regs" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "uart_regs" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../src/uart_transmitter.v 1 1 " "Info: Found 1 design units and 1 entities in source file ../src/uart_transmitter.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_transmitter " "Info: Found entity 1: uart_transmitter" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" "uart_transmitter" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_transmitter.v" 8 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(319) " "Warning: Verilog HDL expression warning at uart_regs.v(319): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 319 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(328) " "Warning: Verilog HDL expression warning at uart_regs.v(328): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 328 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(337) " "Warning: Verilog HDL expression warning at uart_regs.v(337): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 337 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(346) " "Warning: Verilog HDL expression warning at uart_regs.v(346): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 346 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(355) " "Warning: Verilog HDL expression warning at uart_regs.v(355): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 355 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(364) " "Warning: Verilog HDL expression warning at uart_regs.v(364): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 364 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 uart_regs.v(373) " "Warning: Verilog HDL expression warning at uart_regs.v(373): truncated operand with size 32 to match size of smaller operand (16)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 373 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 uart_regs.v(375) " "Warning: Verilog HDL expression warning at uart_regs.v(375): truncated operand with size 32 to match size of smaller operand (16)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 375 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 uart_regs.v(400) " "Warning: Verilog HDL expression warning at uart_regs.v(400): truncated operand with size 32 to match size of smaller operand (8)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 400 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(455) " "Warning: Verilog HDL expression warning at uart_regs.v(455): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 455 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(462) " "Warning: Verilog HDL expression warning at uart_regs.v(462): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 462 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 uart_regs.v(469) " "Warning: Verilog HDL expression warning at uart_regs.v(469): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" "" "" { Text "f:/fan/quatus_word/example-b3-1/uart_regs/src/uart_regs.v" 469 0 0 } }  } 0}