`timescale 1ns / 1ps

module test_txsystem_v;

	// Inputs
	reg clock;
	reg reset;
	reg odd_noteven;
	reg write;
	reg [7:0] datain;

	// Outputs
	wire busy;
	wire txdata;

	// Instantiate the Unit Under Test (UUT)
	txsys uut (
		.clock(clock), 
		.reset(reset), 
		.odd_noteven(odd_noteven), 
		.write(write), 
		.datain(datain), 
		.busy(busy), 
		.txdata(txdata)
	);

	//generate a 32768Hz clock
	initial
	begin
		forever begin
			clock = 0;
			#15259;
			clock = 1;
			#15259;
		end
	end

	initial begin
		reset = 1;
		odd_noteven = 0;
		write = 1;
		datain = 8'h6A;
		@(negedge clock);	  //wait for 1->0 on clock
		reset = 0;
		repeat (3) @(negedge clock);	//wait for 3 (1->0)'s on clock
		write = 0;		  //write data and start transmission
		repeat (3) @(negedge clock);
		write = 1;
		@(negedge busy);	  //wait for 1->0 on busy
		repeat (10) @(negedge clock);
		$stop;
	end
      
endmodule