////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1.04i
//  \   \         Application : ISE Foundation
//  /   /         Filename : test_cntr4.tfw
// /___/   /\     Timestamp : Wed Feb 21 15:14:15 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: test_cntr4
//Device: Xilinx
//
`timescale 1ns/1ps

module test_cntr4;
    reg clock = 1'b0;
    reg reset = 1'b1;
    wire [3:0] count;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clock
    begin
        #OFFSET;
        forever
        begin
            clock = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clock = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    cntr4 UUT (
        .clock(clock),
        .reset(reset),
        .count(count));

        integer TX_ERROR = 0;
        
        initial begin  // Open the results file...
            #5200 // Final time:  5200 ns
            if (TX_ERROR == 0) begin
                $display("No errors or warnings.");
                end else begin
                    $display("%d errors found in simulation.", TX_ERROR);
                    end
                    $stop;
                end

                initial begin
                    // -------------  Current Time:  285ns
                    #285;
                    reset = 1'b0;
                    // -------------------------------------
                    // -------------  Current Time:  3485ns
                    #3200;
                    reset = 1'b1;
                    // -------------------------------------
                    // -------------  Current Time:  3685ns
                    #200;
                    reset = 1'b0;
                    // -------------------------------------
                end

                task CHECK_count;
                    input [3:0] NEXT_count;

                    #0 begin
                        if (NEXT_count !== count) begin
                            $display("Error at time=%dns count=%b, expected=%b", $time, count, NEXT_count);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask

            endmodule