# ISim flow : Creating project file
mag4comp_stx.prj
mag4comp.isim_stx_prj
work
# ISim : Check Syntax for Simulation
*.auxlib
isim
isim_temp
xilinxsim.ini
mag4comp.isim_stx_sim
# ISim flow : Creating project file
mag4comp_stx.prj
mag4comp.isim_stx_prj
work
# ISim : Check Syntax for Simulation
*.auxlib
isim
isim_temp
xilinxsim.ini
mag4comp.isim_stx_sim
# ISim flow : Creating project file
mag4comp_stx.prj
mag4comp.isim_stx_prj
work
# ISim : Check Syntax for Simulation
*.auxlib
isim
isim_temp
xilinxsim.ini
mag4comp.isim_stx_sim
ProjNav -> New -> Test Fixture
__projnav/createTF.err
# ISim flow : Creating project file
test_mag4comp_v_stx.prj
test_mag4comp_v.isim_stx_prj
work
# ISim : Check Syntax
*.auxlib
isim
isim_temp
xilinxsim.ini
test_mag4comp_v.isim_stx
# ISim flow : Creating project file
test_mag4comp_v_beh.prj
test_mag4comp_v.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_mag4comp_v_beh.prj
test_mag4comp_v_isim_beh.exe
test_mag4comp_v.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_mag4comp_v_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test_mag4comp_v.isim_beh_log
isim.hdlsourcefiles
# ISim flow : Creating project file
cntr4_stx.prj
cntr4.isim_stx_prj
work
# ISim : Check Syntax for Simulation
*.auxlib
isim
isim_temp
xilinxsim.ini
cntr4.isim_stx_sim
# Bencher : Creating project file
test_cntr4_bencher.prj
# ProjNav -> New Source -> TBW
test_cntr4.vhw
test_cntr4.ano
test_cntr4.tfw
test_cntr4.ant
# Bencher : Creating project file
test_cntr4_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_cntr4_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_cntr4_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test_cntr4.vhw
test_cntr4.ano
test_cntr4.tfw
test_cntr4.ant
# ISim flow : Creating project file
test_cntr4_beh.prj
test_cntr4.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_cntr4_beh.prj
test_cntr4_isim_beh.exe
test_cntr4.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_cntr4_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test_cntr4.isim_beh_log
isim.hdlsourcefiles
# Bencher : Creating project file
test_cntr4_bencher.prj
# Bencher : Creating project file
test_cntr4_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_cntr4_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test_cntr4.vhw
test_cntr4.ano
test_cntr4.tfw
test_cntr4.ant
# ISim flow : Creating project file
test_cntr4_beh.prj
test_cntr4.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_cntr4_beh.prj
test_cntr4_isim_beh.exe
test_cntr4.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_cntr4_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test_cntr4.isim_beh_log
isim.hdlsourcefiles
# Verilog : Create Schematic Symbol
cntr4.spl
__projnav/jhdparse.log
# Verilog : Create Schematic Symbol
mag4comp.spl
__projnav/jhdparse.log
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : PDCL (jhdparse)
__projnav/pwm_sch_jhdparse_tcl.rsp
# Schematic : View HDL Functional Model
pwm_sch.vf
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# ProjNav -> New Source -> TBW
test_pwm_sch.vhw
test_pwm_sch.ano
test_pwm_sch.tfw
test_pwm_sch.ant
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
test_pwm_sch.vhw
test_pwm_sch.ano
test_pwm_sch.tfw
test_pwm_sch.ant
# ISim flow : Creating project file
test_pwm_sch_beh.prj
test_pwm_sch.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_pwm_sch_beh.prj
test_pwm_sch_isim_beh.exe
test_pwm_sch.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_pwm_sch_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test_pwm_sch.isim_beh_log
isim.hdlsourcefiles
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ISim flow : Creating project file
test_pwm_sch_beh.prj
test_pwm_sch.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_pwm_sch_beh.prj
test_pwm_sch_isim_beh.exe
test_pwm_sch.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_pwm_sch_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test_pwm_sch.isim_beh_log
isim.hdlsourcefiles
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher : Creating project file
test_pwm_sch_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# ISim flow : Creating project file
test_pwm_sch_beh.prj
test_pwm_sch.isim_beh_prj
work
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_pwm_sch_beh.prj
test_pwm_sch_isim_beh.exe
test_pwm_sch.isim_beh_exe
isim
*.auxlib
isim.tmp_save
xilinxsim.ini
# ISim : Simulate Behavioral Model
ISIM_FILE_CPF
test_pwm_sch_beh.prj
isim.cmd
genExpectedResults.cmd
isim
isim.log
isimwavedata.xwv
test_pwm_sch.isim_beh_log
isim.hdlsourcefiles