LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ch is                           --對應于數碼管片選信號，將相應數據送出，檔位通過數碼管顯示
   port(sel:in std_logic_vector(2 downto 0);
        a3,a2,a1,a0,dang:in std_logic_vector(3 downto 0);
        q:out std_logic_vector(3 downto 0));
end ch;
architecture ch_arc of ch is
begin 
  process(sel)
  begin
    case sel is
      when "000" =>q<=a0;
      when "001" =>q<=a1;
      when "010" =>q<=a2;
      when "011" =>q<=a3;
      when "111" =>q<=dang;
      when others =>q<="1111";
    end case;
   end process;
end ch_arc;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity corna is                             --在1S內對被測信號計數的功能，并通過選擇輸出數據實現自動換擋
   port(clr,sig,door:in std_logic;
        alm:out std_logic;
        q3,q2,q1,q0,dang:out std_logic_vector(3 downto 0));
end corna;
architecture corna_arc of corna is 
begin
   process(door,sig)
   variable c0,c1,c2,c3,c4,c5,c6:std_logic_vector(3 downto 0);
   variable x:std_logic;
begin
  if sig'event and sig='1' then
     if door='1' then     --在1s內對被測信號計數
       if c0<"1001" then
          c0:=c0+1;
       else
          c0:="0000";
          if c1<"1001" then
             c1:=c1+1;
          else        
             c1:="0000";
             if c2<"1001" then
                c2:=c2+1;
             else
                c2:="0000";
                if c3<"1001" then
                   c3:=c3+1;
                else
                   c3:="0000";
                   if c4<"1001" then
                      c4:=c4+1;
                   else
                      c4:="0000";
                      if c5<"1001" then
                         c5:=c5+1;
                      else
                         c5:="0000";
                         if c6<"1001" then
                            c6:=c6+1;
                         else
                            c6:="0000";
                            alm<='1';       --若超量程則報警
                         end if;    
                      end if;
                   end if; 
                end if;
             end if;
          end if;
       end if;
    else
       if clr='0' then
           alm<='0';                  --clr鍵用于清除報警信號
       end if;
       c6:="0000";
       c5:="0000";  
       c4:="0000";
       c3:="0000";
       c2:="0000";
       c1:="0000"; 
       c0:="0000"; 
    end if;
    if c6/="0000" then               --若c6不為0，則選擇4檔
       q3<=c6;
       q2<=c5;
       q1<=c4;
       q0<=c3; 
       dang<="0100";
    elsif c5/="0000" then             --否則若c5不為0，則選擇3檔
       q3<=c5;
       q2<=c4;
       q1<=c3;
       q0<=c2;
       dang<="0011";
    elsif c4/="0000" then            --選擇2檔
       q3<=c4;
       q2<=c3;
       q1<=c2;
       q0<=c1;
       dang<="0010";   
    else                --選擇1檔
       q3<=c3;
       q2<=c2;
       q1<=c1;
       q0<=c0;
       dang<="0001";
     end if;
   end if;
 end process;
end corna_arc;
          
          
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity disp is                --七段顯示譯碼器 
   port(d:in std_logic_vector(3 downto 0);
        q:out std_logic_vector(6 downto 0));
end disp;
architecture disp_arc of disp is
begin 
   process(d)
begin
   case d is
      when"0000" =>q<="0111111";
      when"0001" =>q<="0000110";
      when"0010" =>q<="1011011";
      when"0011" =>q<="1001111";
      when"0100" =>q<="1100110";
      when"0101" =>q<="1101101";
      when"0110" =>q<="0111101";
      when"0111" =>q<="0100111";
      when"1000" =>q<="1111111";
      when"1001" =>q<="1101111";
      when others =>q<="0000000";
   end case;
 end process;
end disp_arc;



LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fen is                            --分頻器  將4MHZ的時鐘分頻得到0.5HZ時鐘，為模塊CORNA提供1s的閘門時間
  port(clk:in std_logic;
       q:out std_logic);
end fen;              
architecture fen_arc of fen is
begin
     process(clk)
     variable cnt:integer range 0 to 3999999;
     variable x:std_logic;
begin
   if clk'event and clk='1' then
     if cnt<3999999 then
        cnt:=cnt+1;
      else
        cnt:=0;
        x:=not x;
      end if;
    end if;
    q<=x;
  end process;
end fen_arc;





LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lock is                  --實現鎖存器的功能，信號L的下降沿來到時將信號A4,A3,A2,A1鎖存
   port(L:in std_logic;
        a4,a3,a2,a1,a0:in std_logic_vector(3 downto 0);
        q4,q3,q2,q1,q0:out std_logic_vector(3 downto 0));
end lock;
architecture lock_arc of lock is
begin
   process(L)
   variable t4,t3,t2,t1,t0:std_logic_vector(3 downto 0);
   begin
     if L'event and L='0' then
       t4:=a4;
       t3:=a3;
       t2:=a2;
       t1:=a1;
       t0:=a0;
     end if;
     q4<=t4; 
     q3<=t3;
     q2<=t2;
     q1<=t1;
     q0<=t0;
   end process;
end lock_arc;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sel is                  --用來產生數碼管的片選信號
   port(clk:in std_logic;
        q:out std_logic_vector(2 downto 0));
end sel;
architecture sel_arc of sel is
begin
   process(clk)
   variable cnt:std_logic_vector(2 downto 0);
   begin
     if clk'event and clk='1' then
        cnt:=cnt+1;
       end if;
       q<=cnt;
    end process;
end sel_arc;