module irda(
    clk,
    rst,
    ir_tx,
    ir_rx,
    led,
    keyin,
    led1
);

input     clk;
input     rst;
input     ir_rx;
input     keyin;
output    ir_tx;
output    led;
output    led1;

reg    [8:0]  cnt;
reg           tx_carrier;
wire          carry;


//generate the 40k carrier
assign  carry=(cnt==9'd329) ? 1'b1 : 1'b0;
always @ (posedge clk or posedge rst)
    if (rst)
        cnt<=9'h000;
    else if(carry)
        cnt<=9'h000;
    else
        cnt<=cnt+1'b1;
        
always @ (posedge clk or posedge rst)
    if (rst)
        tx_carrier<=1'b0;
    else if (carry)
        tx_carrier<=~tx_carrier;
    else
        tx_carrier<=tx_carrier;
        
//assign ir_tx=(keyin) ? tx_carrier : 1'b0;
assign ir_tx=1'b0;
assign led=keyin;        
assign led1=ir_rx;
endmodule