?? rightshift.vhd
字號:
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity rightshift is
port(
Din: in std_logic_vector(15 downto 0);
clk: in std_logic;
Dout: out std_logic_vector(15 downto 0));
end entity rightshift;
architecture beha of rightshift is
begin
process(clk)
begin
if(rising_edge(clk)) then
Dout(11 downto 0)<=Din(15 downto 4);
Dout(15 downto 12)<="0000";
end if;
end process;
end beha;
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