library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity koggeStone_32 is    Port ( a : in  STD_LOGIC_VECTOR (31 downto 0);           b : in  STD_LOGIC_VECTOR (31 downto 0);		   ci : in  STD_LOGIC;		   co : out  STD_LOGIC;           s : out  STD_LOGIC_VECTOR (31 downto 0));end koggeStone_32 ;architecture Behavioral of koggeStone_32 is		component halfadder 	port (a, b: in std_logic;sum, carry: out std_logic);	end component;			component fulladder 	port (In1, In2, c_in: in std_logic;         sum, c_out : out std_logic ; p,g : out std_logic);	end component;		-- define the XOR	component xor_2 	GENERIC ( delay : TIME := 2 NS);    PORT (in_1, in_2 : IN STD_LOGIC; out_1 : OUT STD_LOGIC); 	end component;		-- define cell	component cell Port ( gn : in STD_LOGIC;	     pn : in  STD_LOGIC;        gb : in  STD_LOGIC;	     pb : in  STD_LOGIC;        go : out  STD_LOGIC;	     po : out  STD_LOGIC);	end component;signal gS0, gS1, gS2,		 gS3, gS4, gS5 : STD_LOGIC_VECTOR (31 downto 0); signal ps0, pS1, ps2,		 pS3, pS4, pS5 : STD_LOGIC_VECTOR (31 downto 0); 		 begin	-- pre-proccessing	oGen_0 : for i in 0 to 31 generate		if_1 : if (i > 0) generate			oHA : halfadder port map (a(i), b(i),pS0(i), gS0(i) );		end generate;		if_2 : if (i = 0) generate			oFA : fulladder port map (a(0), b(0), ci, open, open,pS0(0),gS0(0));		end generate;	end generate;		-- level 1	oGen_1 : for i in 0 to 31 generate		if_1 : if i = 0 generate			gs1(i) <= gs0(i); ps1(i) <= ps0(i);		end generate;		if_2 : if not(i = 0) generate			ocell : cell port map (gs0(i), ps0(i),				gs0(i-1), ps0(i-1), gs1(i), ps1(i));		end generate;	end generate;		-- level 2	oGen_2 : for i in 0 to 31 generate		if_1 : if i < 2 generate			gs2(i) <= gs1(i); ps2(i) <= ps1(i);		end generate;		if_2 : if i > 1 generate			ocell : cell port map (gs1(i), ps1(i),				gs1(i-2), ps1(i-2), gs2(i), ps2(i));		end generate;	end generate;		-- level 3	oGen_3 : for i in 0 to 31 generate		if_1 : if i < 4 generate			gs3(i) <= gs2(i); ps3(i) <= ps2(i);		end generate;		if_2 : if i > 3 generate			ocell : cell port map (gs2(i), ps2(i),				gs2(i-4), ps2(i-4), gs3(i), ps3(i));		end generate;	end generate;		-- level 4	oGen_4 : for i in 0 to 31 generate		if_1 : if i < 8 generate			gs4(i) <= gs3(i); ps4(i) <= ps3(i);		end generate;		if_2 : if i > 7 generate			ocell : cell port map (gs3(i), ps3(i),				gs3(i-8), ps3(i-8), gs4(i), ps4(i));		end generate;	end generate;		-- level 5	oGen_5 : for i in 0 to 31 generate		if_1 : if i < 16 generate			gs5(i) <= gs4(i); ps5(i) <= ps4(i);		end generate;		if_2 : if i > 15 generate			ocell : cell port map (gs4(i), ps4(i),				gs4(i-16), ps4(i-16), gs5(i), ps5(i));		end generate;	end generate;			-- post-proccessing	xoring : xor_2 port map (ci, ps0(0), s(0));	oGen_6 : for i in 1 to 31 generate		xoring : xor_2 port map (gs5(i-1), ps0(i), s(i));	end generate;	co <= gs5(31);	end Behavioral;