;     -- Combinational with no register       ; 1                 ;
;     -- Register only                        ; 12                ;
;     -- Combinational with a register        ; 3                 ;
;                                             ;                   ;
; Logic element usage by number of LUT inputs ;                   ;
;     -- 4 input functions                    ; 0                 ;
;     -- 3 input functions                    ; 2                 ;
;     -- 2 input functions                    ; 2                 ;
;     -- 1 input functions                    ; 0                 ;
;     -- 0 input functions                    ; 0                 ;
;         -- Combinational cells for routing  ; 0                 ;
;                                             ;                   ;
; Logic elements by mode                      ;                   ;
;     -- normal mode                          ; 16                ;
;     -- arithmetic mode                      ; 0                 ;
;     -- qfbk mode                            ; 0                 ;
;     -- register cascade mode                ; 0                 ;
;     -- synchronous clear/load mode          ; 0                 ;
;     -- asynchronous clear/load mode         ; 0                 ;
;                                             ;                   ;
; Total registers                             ; 15                ;
; I/O pins                                    ; 23                ;
; Maximum fan-out node                        ; current_state.st6 ;
; Maximum fan-out                             ; 11                ;
; Total fan-out                               ; 49                ;
; Average fan-out                             ; 1.26              ;
+---------------------------------------------+-------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |adcint                    ; 16 (16)     ; 15           ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 23   ; 0            ; 1 (1)        ; 12 (12)           ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |adcint             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |adcint|current_state                                                                                                                         ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; Name              ; current_state.st6 ; current_state.st5 ; current_state.st4 ; current_state.st3 ; current_state.st2 ; current_state.st1 ; current_state.st0 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+
; current_state.st0 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ;
; current_state.st1 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 1                 ;
; current_state.st2 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 1                 ;
; current_state.st3 ; 0                 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 1                 ;
; current_state.st4 ; 0                 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; current_state.st5 ; 0                 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
; current_state.st6 ; 1                 ; 0                 ; 0                 ; 0                 ; 0                 ; 0                 ; 1                 ;
+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+-------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 15    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; current_state.st0                      ; 1       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+---------------------------------------------------+
; Source assignments for Top-level Entity: |ADCINT  ;
+----------------+-------+------+-------------------+
; Assignment     ; Value ; From ; To                ;
+----------------+-------+------+-------------------+
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st6 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st5 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st4 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st3 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st2 ;
; POWER_UP_LEVEL ; Low   ; -    ; current_state.st1 ;
; POWER_UP_LEVEL ; High  ; -    ; current_state.st0 ;
+----------------+-------+------+-------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sat Apr 11 20:49:00 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADCINT -c ADCINT
Info: Found 2 design units, including 1 entities, in source file ADCINT.vhd
    Info: Found design unit 1: ADCINT-ONE
    Info: Found entity 1: adcint
Info: Elaborating entity "ADCINT" for the top level hierarchy
Info: State machine "|adcint|current_state" contains 7 states
Info: Selected Auto state machine encoding method for state machine "|adcint|current_state"
Info: Encoding result for state machine "|adcint|current_state"
    Info: Completed encoding using 7 state bits
        Info: Encoded state bit "current_state.st6"
        Info: Encoded state bit "current_state.st5"
        Info: Encoded state bit "current_state.st4"
        Info: Encoded state bit "current_state.st3"
        Info: Encoded state bit "current_state.st2"
        Info: Encoded state bit "current_state.st1"
        Info: Encoded state bit "current_state.st0"
    Info: State "|adcint|current_state.st0" uses code string "0000000"
    Info: State "|adcint|current_state.st1" uses code string "0000011"
    Info: State "|adcint|current_state.st2" uses code string "0000101"
    Info: State "|adcint|current_state.st3" uses code string "0001001"
    Info: State "|adcint|current_state.st4" uses code string "0010001"
    Info: State "|adcint|current_state.st5" uses code string "0100001"
    Info: State "|adcint|current_state.st6" uses code string "1000001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ADDA" stuck at VCC
Info: Implemented 39 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 13 output pins
    Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Apr 11 20:49:01 2009
    Info: Elapsed time: 00:00:02