Simulator report for sreg8b
Mon Dec 31 11:30:33 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Simulator INI Usage
  6. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 300.0 us     ;
; Simulation Netlist Size     ; 72 nodes     ;
; Simulation Coverage         ;       6.90 % ;
; Total Number of Transitions ; 666          ;
+-----------------------------+--------------+


+---------------------------------------------------------------------------------------------+
; Simulator Settings                                                                          ;
+-------------------------------------------------------+-------------------------------------+
; Option                                                ; Setting                             ;
+-------------------------------------------------------+-------------------------------------+
; Simulation mode                                       ; Timing                              ;
; Start time                                            ; 0ns                                 ;
; Vector input source                                   ; D:/eda設計/VHDL/乘法器/multi8x8.vwf ;
; Add pins automatically to simulation output waveforms ; On                                  ;
; Check outputs                                         ; Off                                 ;
; Report simulation coverage                            ; On                                  ;
; Detect setup and hold time violations                 ; Off                                 ;
; Detect glitches                                       ; Off                                 ;
; Automatically save/load simulation netlist            ; Off                                 ;
; Disable timing delays in Timing Simulation            ; Off                                 ;
; Generate Signal Activity File                         ; Off                                 ;
+-------------------------------------------------------+-------------------------------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Dec 31 11:30:32 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off sreg8b -c sreg8b
Info: Simulation coverage is       6.90 %
Info: Number of transitions in simulation is 666
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Dec 31 11:30:33 2007
    Info: Elapsed time: 00:00:01