?? crc.tan.rpt
字號:
Timing Analyzer report for CRC
Thu Mar 22 14:49:26 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Minimum tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+---------------+-------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+---------------+-------------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 13.699 ns ; data_check[4] ; s[2] ; -- ; -- ; 0 ;
; Worst-case Minimum tpd ; N/A ; None ; 10.755 ns ; choice ; data_CRC[2] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+---------------+-------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C6Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; On ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+---------------+-------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+---------------+-------------+
; N/A ; None ; 13.699 ns ; data_check[4] ; s[2] ;
; N/A ; None ; 13.530 ns ; data_in[2] ; data_CRC[2] ;
; N/A ; None ; 13.527 ns ; data_check[4] ; s[1] ;
; N/A ; None ; 13.441 ns ; data_check[5] ; s[2] ;
; N/A ; None ; 13.405 ns ; data_in[1] ; data_CRC[2] ;
; N/A ; None ; 13.363 ns ; data_check[5] ; s[0] ;
; N/A ; None ; 13.335 ns ; data_check[6] ; s[2] ;
; N/A ; None ; 13.271 ns ; data_check[5] ; s[1] ;
; N/A ; None ; 13.147 ns ; data_check[6] ; s[0] ;
; N/A ; None ; 13.122 ns ; data_in[2] ; data_CRC[0] ;
; N/A ; None ; 13.030 ns ; data_in[3] ; data_CRC[2] ;
; N/A ; None ; 12.995 ns ; data_in[1] ; data_CRC[1] ;
; N/A ; None ; 12.846 ns ; data_in[0] ; data_CRC[0] ;
; N/A ; None ; 12.844 ns ; data_in[0] ; data_CRC[1] ;
; N/A ; None ; 12.710 ns ; data_in[2] ; data_CRC[5] ;
; N/A ; None ; 12.710 ns ; data_in[0] ; data_CRC[3] ;
; N/A ; None ; 12.706 ns ; data_in[3] ; data_CRC[6] ;
; N/A ; None ; 12.686 ns ; data_check[3] ; s[1] ;
; N/A ; None ; 12.632 ns ; data_in[2] ; data_CRC[1] ;
; N/A ; None ; 12.622 ns ; data_in[3] ; data_CRC[0] ;
; N/A ; None ; 12.583 ns ; data_in[1] ; data_CRC[4] ;
; N/A ; None ; 12.560 ns ; data_check[3] ; s[0] ;
; N/A ; None ; 12.541 ns ; data_check[2] ; s[2] ;
; N/A ; None ; 12.508 ns ; data_check[0] ; s[0] ;
; N/A ; None ; 12.178 ns ; choice ; s[2] ;
; N/A ; None ; 12.169 ns ; choice ; s[1] ;
; N/A ; None ; 12.153 ns ; choice ; s[0] ;
; N/A ; None ; 12.036 ns ; data_check[1] ; s[1] ;
; N/A ; None ; 11.208 ns ; choice ; data_CRC[6] ;
; N/A ; None ; 11.198 ns ; choice ; data_CRC[4] ;
; N/A ; None ; 11.193 ns ; choice ; data_CRC[3] ;
; N/A ; None ; 10.954 ns ; choice ; data_CRC[5] ;
; N/A ; None ; 10.762 ns ; choice ; data_CRC[1] ;
; N/A ; None ; 10.762 ns ; choice ; data_CRC[0] ;
; N/A ; None ; 10.755 ns ; choice ; data_CRC[2] ;
+-------+-------------------+-----------------+---------------+-------------+
+-----------------------------------------------------------------------------------+
; Minimum tpd ;
+---------------+-------------------+-----------------+---------------+-------------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+---------------+-------------+
; N/A ; None ; 10.755 ns ; choice ; data_CRC[2] ;
; N/A ; None ; 10.762 ns ; choice ; data_CRC[0] ;
; N/A ; None ; 10.762 ns ; choice ; data_CRC[1] ;
; N/A ; None ; 10.954 ns ; choice ; data_CRC[5] ;
; N/A ; None ; 11.193 ns ; choice ; data_CRC[3] ;
; N/A ; None ; 11.198 ns ; choice ; data_CRC[4] ;
; N/A ; None ; 11.208 ns ; choice ; data_CRC[6] ;
; N/A ; None ; 12.036 ns ; data_check[1] ; s[1] ;
; N/A ; None ; 12.153 ns ; choice ; s[0] ;
; N/A ; None ; 12.169 ns ; choice ; s[1] ;
; N/A ; None ; 12.178 ns ; choice ; s[2] ;
; N/A ; None ; 12.508 ns ; data_check[0] ; s[0] ;
; N/A ; None ; 12.541 ns ; data_check[2] ; s[2] ;
; N/A ; None ; 12.560 ns ; data_check[3] ; s[0] ;
; N/A ; None ; 12.583 ns ; data_in[1] ; data_CRC[4] ;
; N/A ; None ; 12.622 ns ; data_in[3] ; data_CRC[0] ;
; N/A ; None ; 12.632 ns ; data_in[2] ; data_CRC[1] ;
; N/A ; None ; 12.686 ns ; data_check[3] ; s[1] ;
; N/A ; None ; 12.706 ns ; data_in[3] ; data_CRC[6] ;
; N/A ; None ; 12.710 ns ; data_in[0] ; data_CRC[3] ;
; N/A ; None ; 12.710 ns ; data_in[2] ; data_CRC[5] ;
; N/A ; None ; 12.844 ns ; data_in[0] ; data_CRC[1] ;
; N/A ; None ; 12.846 ns ; data_in[0] ; data_CRC[0] ;
; N/A ; None ; 12.995 ns ; data_in[1] ; data_CRC[1] ;
; N/A ; None ; 13.030 ns ; data_in[3] ; data_CRC[2] ;
; N/A ; None ; 13.122 ns ; data_in[2] ; data_CRC[0] ;
; N/A ; None ; 13.147 ns ; data_check[6] ; s[0] ;
; N/A ; None ; 13.271 ns ; data_check[5] ; s[1] ;
; N/A ; None ; 13.335 ns ; data_check[6] ; s[2] ;
; N/A ; None ; 13.363 ns ; data_check[5] ; s[0] ;
; N/A ; None ; 13.405 ns ; data_in[1] ; data_CRC[2] ;
; N/A ; None ; 13.441 ns ; data_check[5] ; s[2] ;
; N/A ; None ; 13.527 ns ; data_check[4] ; s[1] ;
; N/A ; None ; 13.530 ns ; data_in[2] ; data_CRC[2] ;
; N/A ; None ; 13.699 ns ; data_check[4] ; s[2] ;
+---------------+-------------------+-----------------+---------------+-------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Mar 22 14:49:26 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CRC -c CRC --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
Warning: Node "data_CRC[0]$latch" is a latch
Warning: Node "data_CRC[1]$latch" is a latch
Warning: Node "data_CRC[2]$latch" is a latch
Warning: Node "data_CRC[3]$latch" is a latch
Warning: Node "data_CRC[4]$latch" is a latch
Warning: Node "data_CRC[5]$latch" is a latch
Warning: Node "data_CRC[6]$latch" is a latch
Warning: Node "s[0]$latch" is a latch
Warning: Node "s[1]$latch" is a latch
Warning: Node "s[2]$latch" is a latch
Info: Found combinational loop of 1 nodes
Info: Node "s[2]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "s[1]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "s[0]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "data_CRC[6]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "data_CRC[5]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "data_CRC[4]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "data_CRC[3]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "data_CRC[2]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "data_CRC[1]$latch"
Info: Found combinational loop of 1 nodes
Info: Node "data_CRC[0]$latch"
Info: Longest tpd from source pin "data_check[4]" to destination pin "s[2]" is 13.699 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_214; Fanout = 2; PIN Node = 'data_check[4]'
Info: 2: + IC(6.017 ns) + CELL(0.590 ns) = 8.082 ns; Loc. = LC_X24_Y20_N9; Fanout = 2; COMB Node = 'reg_t~160'
Info: 3: + IC(0.000 ns) + CELL(1.014 ns) = 9.096 ns; Loc. = LC_X24_Y20_N5; Fanout = 2; COMB LOOP Node = 's[2]$latch'
Info: Loc. = LC_X24_Y20_N5; Node "s[2]$latch"
Info: 4: + IC(2.479 ns) + CELL(2.124 ns) = 13.699 ns; Loc. = PIN_175; Fanout = 0; PIN Node = 's[2]'
Info: Total cell delay = 5.203 ns ( 37.98 % )
Info: Total interconnect delay = 8.496 ns ( 62.02 % )
Info: Shortest tpd from source pin "choice" to destination pin "data_CRC[2]" is 10.755 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_12; Fanout = 20; PIN Node = 'choice'
Info: 2: + IC(0.000 ns) + CELL(5.834 ns) = 7.303 ns; Loc. = LC_X1_Y7_N2; Fanout = 2; COMB LOOP Node = 'data_CRC[2]$latch'
Info: Loc. = LC_X1_Y7_N2; Node "data_CRC[2]$latch"
Info: 3: + IC(1.328 ns) + CELL(2.124 ns) = 10.755 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'data_CRC[2]'
Info: Total cell delay = 9.427 ns ( 87.65 % )
Info: Total interconnect delay = 1.328 ns ( 12.35 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 11 warnings
Info: Processing ended: Thu Mar 22 14:49:26 2007
Info: Elapsed time: 00:00:01
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