LIBRARY IEEE;  --測頻控制
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ctrl IS
   PORT(CLKK:IN STD_LOGIC; --時鐘1HZ
       CNT_EN:OUT STD_LOGIC; --使能
       RST_CNT:OUT STD_LOGIC; --清零
        LOAD:OUT STD_LOGIC); --輸出鎖存信號 
END ctrl;

ARCHITECTURE behav OF ctrl IS
  SIGNAL Div2CLK:STD_LOGIC;
  BEGIN
  PROCESS(CLKK)
    BEGIN
      IF CLKK'EVENT AND CLKK='1' THEN
         Div2CLK<= NOT Div2CLK;
      END IF;
  END PROCESS;
  PROCESS(CLKK,Div2CLK)
    BEGIN
      IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1'; --產生計數器清零信號
      ELSE RST_CNT<='0';
      END IF;
  END PROCESS;
  LOAD<=NOT Div2CLK;
  CNT_EN<=Div2CLK;
END behav;