; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
; jk_ff.v                          ; yes             ; Other     ; F:/qutus/jk_ff/jk_ff.v       ;
+----------------------------------+-----------------+-----------+------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimated Total logic elements              ; 2       ;
;                                             ;         ;
; Total combinational functions               ; 2       ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 1       ;
;     -- 3 input functions                    ; 0       ;
;     -- <=2 input functions                  ; 1       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 2       ;
;     -- arithmetic mode                      ; 0       ;
;                                             ;         ;
; Total registers                             ; 0       ;
;     -- Dedicated logic registers            ; 0       ;
;     -- I/O registers                        ; 0       ;
;                                             ;         ;
; I/O pins                                    ; 6       ;
; Maximum fan-out node                        ; Mux0~35 ;
; Maximum fan-out                             ; 2       ;
; Total fan-out                               ; 7       ;
; Average fan-out                             ; 0.88    ;
+---------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |jk_ff                     ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 6    ; 0            ; |jk_ff              ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; q~2                                                    ;   ;
; Number of logic cells representing combinational loops ; 1 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Mon Mar 30 21:41:38 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jk_ff -c jk_ff
Warning: Using design file jk_ff.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: jk_ff
Info: Elaborating entity "jk_ff" for the top level hierarchy
Warning (10755): Verilog HDL warning at jk_ff.v(5): assignments to q create a combinational loop
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "clk"
Info: Implemented 8 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 1 output pins
    Info: Implemented 2 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 133 megabytes of memory during processing
    Info: Processing ended: Mon Mar 30 21:41:39 2009
    Info: Elapsed time: 00:00:01