#
# This class.ptf file built by Component Editor
# 2006.11.20.18:19:46
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS pwm_avalon_interface
{
   CB_GENERATOR 
   {
      HDL_FILES 
      {
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "verilog";
            filepath = "hdl/pwm_avalon_interface.v";
         }
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "verilog";
            filepath = "hdl/pwm_register_file.v";
         }
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "verilog";
            filepath = "hdl/pwm_task_logic.v";
         }
      }
      top_module_name = "pwm_avalon_interface.v:pwm_avalon_interface";
      emit_system_h = "0";
      LIBRARIES 
      {
      }
   }
   MODULE_DEFAULTS global_signals
   {
      class = "pwm_avalon_interface";
      class_version = "1.0 Build by tenglong";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Has_Clock = "0";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      PORT_WIRING 
      {
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         hdl_parameters 
         {
            clock_divide_reg_init = "32'b00000000000000000000000000000000";
            duty_cycle_reg_init = "32'b00000000000000000000000000000000";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
         }
      }
      SLAVE control_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "1";
            Has_Clock = "1";
            Address_Width = "2";
            Address_Alignment = "native";
            Data_Width = "32";
            Has_Base_Address = "1";
            Has_IRQ = "0";
            Setup_Time = "0cycles";
            Hold_Time = "0cycles";
            Read_Wait_States = "0cycles";
            Write_Wait_States = "0cycles";
            Read_Latency = "0";
            Maximum_Pending_Read_Transactions = "0";
            Active_CS_Through_Read_Latency = "0";
            Is_Printable_Device = "0";
            Is_Memory_Device = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            Minimum_Uninterrupted_Run_Length = "1";
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "0";
               Read_Wait_Value = "0";
               Write_Wait_Value = "0";
               Hold_Value = "0";
               Timing_Units = "cycles";
               Read_Latency_Value = "0";
               Minimum_Arbitration_Shares = "1";
               Active_CS_Through_Read_Latency = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "native";
               Is_Printable_Device = "0";
               Interleave_Bursts = "0";
               interface_name = "Avalon Slave";
               external_wait = "0";
               Is_Memory_Device = "0";
            }
         }
         PORT_WIRING 
         {
            PORT clk
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "clk";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT resetn
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "reset_n";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT avalon_chip_select
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "chipselect";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT address
            {
               width = "2";
               width_expression = "";
               direction = "input";
               type = "address";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT write
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "write";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT write_data
            {
               width = "32";
               width_expression = "";
               direction = "input";
               type = "writedata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT read
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "read";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT read_data
            {
               width = "32";
               width_expression = "";
               direction = "output";
               type = "readdata";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
            PORT pwm_out
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
               is_shared = "0";
               vhdl_record_name = "";
               vhdl_record_type = "";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "pwm_avalon_interface";
         technology = "tenglong";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "pwm_avalon_interface - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_global_signals = "SYSTEM_BUILDER_INFO";
            SBI_control_slave = "SLAVE control_slave/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>pwm_avalon_interface 1.0</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2006.11.20.18:19:46";
               }
               TEXT 
               {
                  title = "Class name: pwm_avalon_interface";
               }
               TEXT 
               {
                  title = "Class version: 1.0";
               }
               TEXT 
               {
                  title = "Component name: pwm_avalon_interface";
               }
               TEXT 
               {
                  title = "Component Group: tenglong";
               }
               GROUP parameters
               {
                  title = "Parameters";
                  layout = "form";
                  align = "left";
                  EDIT e1
                  {
                     id = "clock_divide_reg_init";
                     editable = "1";
                     title = "clock_divide_reg_init:";
                     columns = "40";
                     tooltip = "default value: 32'b00000000000000000000000000000000";
                     DATA 
                     {
                        $H/clock_divide_reg_init = "$";
                     }
                     q = "'";
                     warning = "{{ if(!(regexp('ugly_'+$H/clock_divide_reg_init,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/clock_divide_reg_init,'ugly_-?[0-9]+')))'clock_divide_reg_init must be numeric constant, not '+$H/clock_divide_reg_init; }}";