---------------------------------------------------------------------------------- Purpose : synthesizable CRC function--   * polynomial: (0 2 5)--   * data width: 8--------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;package PCK_CRC5_D8 is  -- polynomial: (0 2 5)  -- data width: 8  -- convention: the first serial bit is D[7]  function nextCRC5_D8    (Data: std_logic_vector(7 downto 0);     crc:  std_logic_vector(4 downto 0))    return std_logic_vector;end PCK_CRC5_D8;package body PCK_CRC5_D8 is  -- polynomial: (0 2 5)  -- data width: 8  -- convention: the first serial bit is D[7]  function nextCRC5_D8    (Data: std_logic_vector(7 downto 0);     crc:  std_logic_vector(4 downto 0))    return std_logic_vector is    variable d:      std_logic_vector(7 downto 0);    variable c:      std_logic_vector(4 downto 0);    variable newcrc: std_logic_vector(4 downto 0);  begin    d := Data;    c := crc;    newcrc(0) := d(6) xor d(5) xor d(3) xor d(0) xor c(0) xor c(2) xor c(3);    newcrc(1) := d(7) xor d(6) xor d(4) xor d(1) xor c(1) xor c(3) xor c(4);    newcrc(2) := d(7) xor d(6) xor d(3) xor d(2) xor d(0) xor c(0) xor c(3) xor c(4);    newcrc(3) := d(7) xor d(4) xor d(3) xor d(1) xor c(0) xor c(1) xor c(4);    newcrc(4) := d(5) xor d(4) xor d(2) xor c(1) xor c(2);    return newcrc;  end nextCRC5_D8;end PCK_CRC5_D8;