library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity demux74155 isport(din: in std_logic;		s: in std_logic_vector(1 downto 0);		y: out std_logic_vector(3 downto 0)		);end demux74155;architecture reg of demux74155 issignal sy: std_logic_vector (3 downto 0);begin	process(din, s)	begin		if (s="00") then sy<="000"& din;		elsif(s="01") then sy<="00"&din &'0';		elsif(s="10") then sy<='0'& din & "00";		else sy<= din & "000";		end if;	end process;	y <= sy;end reg;