?? siva.cr.mti
字號:
D:/myhdl/and3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/and3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity andgate3
-- Compiling architecture reg of andgate3
} {} {}} D:/myhdl/comp7485.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/comp7485.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity comp7485
-- Compiling architecture reg of comp7485
} {} {}} D:/myhdl/nor2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/nor2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity norgate2
-- Compiling architecture reg of norgate2
} {} {}} D:/myhdl/nor3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/nor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity norgate3
-- Compiling architecture reg of norgate3
} {} {}} D:/myhdl/beor2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/beor2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity borgate2
-- Compiling architecture reg of borgate2
} {} {}} D:/myhdl/bexor2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/bexor2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bxorgate2
-- Compiling architecture reg of bxorgate2
} {} {}} D:/myhdl/notgate.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/notgate.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity notgate
-- Compiling architecture reg of notgate
} {} {}} D:/myhdl/bexor3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/bexor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bxorgate3
-- Compiling architecture reg of bxorgate3
} {} {}} D:/myhdl/beor3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/beor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity borgate3
-- Compiling architecture reg of borgate3
} {} {}} E:/myhdl/benand2.vhd {1 {vcom -work work -2002 -explicit E:/myhdl/benand2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bnandgate2
-- Compiling architecture reg of bnandgate2
} {} {}} D:/myhdl/or2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/or2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity orgate2
-- Compiling architecture reg of orgate2
} {} {}} E:/myhdl/bexor3.vhd {1 {vcom -work work -2002 -explicit E:/myhdl/bexor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bxorgate3
-- Compiling architecture reg of bxorgate3
} {} {}} D:/myhdl/beand2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/beand2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bandgate2
-- Compiling architecture reg of bandgate2
} {} {}} D:/myhdl/or3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/or3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity orgate3
-- Compiling architecture reg of orgate3
} {} {}} E:/myhdl/nand3.vhd {1 {vcom -work work -2002 -explicit E:/myhdl/nand3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity nandgate3
-- Compiling architecture reg of nandgate3
} {} {}} D:/myhdl/beand3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/beand3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bandgate3
-- Compiling architecture reg of bandgate3
} {} {}} D:/myhdl/dec7418.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/dec7418.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity dec74138
-- Compiling architecture reg of dec74138
} {} {}} D:/myhdl/bexnor2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/bexnor2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bxnorgate2
-- Compiling architecture reg of bxnorgate2
} {} {}} D:/myhdl/benor2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/benor2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bnorgate2
-- Compiling architecture reg of bnorgate2
} {} {}} D:/myhdl/demux74155.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/demux74155.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity demux74155
-- Compiling architecture reg of demux74155
} {} {}} D:/myhdl/benor3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/benor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bnorgate3
-- Compiling architecture reg of bnorgate3
} {} {}} D:/myhdl/bexnor3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/bexnor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bxnorgate3
-- Compiling architecture reg of bxnorgate3
} {} {}} D:/myhdl/xnor2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/xnor2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity xnorgate2
-- Compiling architecture reg of xnorgate2
} {} {}} D:/myhdl/xnor3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/xnor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity xnorgate3
-- Compiling architecture reg of xnorgate3
} {} {}} D:/myhdl/benand2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/benand2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bnandgate2
-- Compiling architecture reg of bnandgate2
} {} {}} D:/myhdl/nand2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/nand2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity nandgate2
-- Compiling architecture reg of nandgate2
} {} {}} E:/myhdl/notgate.vhd {1 {vcom -work work -2002 -explicit E:/myhdl/notgate.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity notgate
-- Compiling architecture reg of notgate
} {} {}} D:/myhdl/unishift74194.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/unishift74194.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity shift74194
-- Compiling architecture reg of shift74194
} {} {}} D:/myhdl/benand3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/benand3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity bnandgate3
-- Compiling architecture reg of bnandgate3
} {} {}} D:/myhdl/xor2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/xor2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity xorgate2
-- Compiling architecture reg of xorgate2
} {} {}} D:/myhdl/mux74151.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/mux74151.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity mux74151
-- Compiling architecture reg of mux74151
} {} {}} D:/myhdl/xor3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/xor3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity xorgate3
-- Compiling architecture reg of xorgate3
} {} {}} D:/myhdl/nand3.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/nand3.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity nandgate3
-- Compiling architecture reg of nandgate3
} {} {}} D:/myhdl/and2.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/and2.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity andgate2
-- Compiling architecture reg of andgate2
} {} {}} D:/myhdl/shiftreg7495.vhd {1 {vcom -work work -2002 -explicit D:/myhdl/shiftreg7495.vhd
Model Technology ModelSim ALTERA vcom 6.3g_p1 Compiler 2008.08 Aug 13 2008
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package std_logic_arith
-- Loading package std_logic_unsigned
-- Compiling entity shift7495
-- Compiling architecture reg of shift7495
} {} {}}
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -