library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity lcd_control is
port(clk:in std_logic;
	rst_n:in std_logic;
	lcd_rs:out std_logic;
	lcd_rw:out std_logic;
	lcd_en:buffer std_logic;
	lcd_data:out std_logic_vector(7 downto 0));
end lcd_control;

architecture one of lcd_control is
component data_rom 
port
(
	address: in std_logic_vector(4 downto 0);
	clock:in std_logic;
	q:out std_logic_vector(7 downto 0)
);
end component;
--***************************************************
signal rs:std_logic;
signal rw:std_logic;
signal en:std_logic;
signal data:std_logic_vector(7 downto 0);
signal showdata:std_logic_vector(7 downto 0);
--**************************************************
signal cnt: std_logic_vector(4 downto 0);
signal cnt_rst:std_logic;
signal div_cnt:std_logic_vector(14 downto 0);
signal clk_div:std_logic;
--***************************************************
signal line_done: std_logic;
signal frame_done:std_logic;
type state_lcdctrl is
( idle,setbase1,setbase2,setmodel1,setmodel2,setcurs1,setcurs2,wr_addr1,wr_addr2,
	wr_data1,wr_data2);

signal current_state,next_state:state_lcdctrl;
--============================================================================
begin
lcd_rs<=rs;
lcd_rw<=rw;
lcd_en<=en;
lcd_data<=data;
--there is no need read data for this programe so RW=0
rw<='0';
--============================================================================
clock_div:process(clk,rst_n)
begin
if rst_n='0' then
div_cnt<=(others=>'0');
elsif clk'event and clk='1' then
	div_cnt<=div_cnt+1;
end if;
end process;
--============================================================================
process(div_cnt)
begin
if (div_cnt=16#7fff#) then
clk_div<='1';
else
clk_div<='0';
end if;
end process;
--===========================================================================
state_turen:process(clk_div,rst_n)
begin
if rst_n='0' then 
current_state<=idle;
elsif (clk_div'event and clk_div='1') then
current_state<=next_state;
end if;
end process;
--==========================================================================
state_com:process(current_state,line_done,frame_done,cnt,showdata)
begin
rs<='0';
en<='0';
cnt_rst<='0';
data<=(others=>'0');
case current_state is
	when idle => next_state<=setbase1;
	when setbase1 => next_state<=setbase2;data<="00110000";en<='1';
	when setbase2 => next_state<=setmodel1;data<="00110000";
	when setmodel1 => next_state<=setmodel2;data<="00000110";en<='1';
	when setmodel2 => next_state<=setcurs1;data<="00000110";
	when setcurs1 => next_state<=setcurs2;data<="00001100";en<='1';
	when setcurs2 => next_state<=wr_addr1;data<="00001100";
	when wr_addr1 => next_state<=wr_addr2;data<="100"&cnt(4)&"0000";
	when wr_addr2 => next_state<=wr_addr1; data<="100"&cnt(4)&"0000";
	when wr_data1 => next_state<=wr_data2;data<=showdata;en<='1';rs<='1';
	when wr_data2=> 
					rs<='1';data<=showdata;
					if(line_done='1') then
					if(frame_done='1') then
					next_state<=idle;
					else
					next_state<=wr_addr1;
					end if;
					else
					next_state<=wr_addr1;
					end if;
	when others => next_state<=idle;
	end case;
	end process;
--====================================================================
cnt_p:process(clk_div,cnt_rst)
begin
if clk_div'event and clk_div='1' then
	if cnt_rst='1' then
	cnt<=(others=>'0');
	elsif (current_state=wr_data2) then
	cnt<=cnt+1;
	end if;
end if;
end process;
--====================================================================
process(cnt)
begin
if (cnt(3 downto 0)="1111") then 
line_done<='1';
else
line_done<='0';
end if;
if(cnt(4)='1') then 
frame_done<='1';
else
frame_done<='0';
end if;
end process;
--=====================================================================
rom1:data_rom port map(address=>cnt,clock=>clk,q=>showdata);
end one;