?? lcd_timing_controller.v
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// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Major Functions: DE2 LTM module Timing control and color pattern
// generator
//
// --------------------------------------------------------------------
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Fan :| 07/06/30 :| Initial Revision
// --------------------------------------------------------------------
module lcd_timing_controller (
iCLK, // LCD display clock
iRST_n, // systen reset
//LCD SIDE
iRed,
iGreen,
iBlue,
oHD, // LCD Horizontal sync
oVD, // LCD Vertical sync
oDEN, // LCD Data Enable
oLCD_R, // LCD Red color data
oLCD_G, // LCD Green color data
oLCD_B, // LCD Blue color data
iDISPLAY_MODE
);
//============================================================================
// PARAMETER declarations
//============================================================================
parameter H_LINE = 1056;
parameter V_LINE = 525;
parameter Hsync_Blank = 216;
parameter Hsync_Front_Porch = 40;
parameter Vertical_Back_Porch = 35;
parameter Vertical_Front_Porch = 10;
//===========================================================================
// PORT declarations
//===========================================================================
input iCLK;
input iRST_n;
input [7:0] iRed;
input [7:0] iGreen;
input [7:0] iBlue;
output [7:0] oLCD_R;
output [7:0] oLCD_G;
output [7:0] oLCD_B;
output oHD;
output oVD;
output oDEN;
input [1:0] iDISPLAY_MODE;
//=============================================================================
// REG/WIRE declarations
//=============================================================================
reg [10:0] x_cnt; // x_cnt >> 11 bits
reg [9:0] y_cnt;
wire [7:0] mred;
wire [7:0] mgreen;
wire [7:0] mblue;
wire display_area;
reg mhd;
reg mvd;
reg mden;
reg oHD;
reg oVD;
reg oDEN;
reg [7:0] oLCD_R;
reg [7:0] oLCD_G;
reg [7:0] oLCD_B;
wire [1:0] msel;
reg [7:0] red_1;
reg [7:0] green_1;
reg [7:0] blue_1;
reg [7:0] graycnt;
reg [7:0] pattern_data;
//=============================================================================
// Structural coding
//=============================================================================
// This signal indicate the lcd(LTM) display area .
assign display_area = ((x_cnt>(Hsync_Blank-1)&& //x_cnt > 215
(x_cnt<(H_LINE-Hsync_Front_Porch))&& //x_cnt < 1016
(y_cnt>(Vertical_Back_Porch-1))&& // y_cnt > 34
(y_cnt<(V_LINE - Vertical_Front_Porch))//y_cnt < 515
)) ? 1'b1 : 1'b0;
///////////////////////// x y counter and lcd hd generator //////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
x_cnt <= 11'd0;
mhd <= 1'd0;
end
else if (x_cnt == (H_LINE-1))
begin
x_cnt <= 11'd0;
mhd <= 1'd0;
end
else
begin
x_cnt <= x_cnt + 11'd1;
mhd <= 1'd1;
end
end
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
y_cnt <= 10'd0;
else if (x_cnt == (H_LINE-1))
begin
if (y_cnt == (V_LINE-1))
y_cnt <= 10'd0;
else
y_cnt <= y_cnt + 10'd1;
end
end
////////////////////////////// touch panel timing //////////////////
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
mvd <= 1'b1;
else if (y_cnt == 10'd0)
mvd <= 1'b0;
else
mvd <= 1'b1;
end
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
mden <= 1'b0;
else if (display_area)
mden <= 1'b1;
else
mden <= 1'b0;
end
assign mred = iRed;
assign mgreen = iGreen;
assign mblue = iBlue;
always@(posedge iCLK or negedge iRST_n)
begin
if (!iRST_n)
begin
oHD <= 1'd0;
oVD <= 1'd0;
oDEN <= 1'd0;
oLCD_R <= 8'd0;
oLCD_G <= 8'd0;
oLCD_B <= 8'd0;
end
else
begin
oHD <= mhd;
oVD <= mvd;
oDEN <= display_area;
oLCD_R <= mred;
oLCD_G <= mgreen;
oLCD_B <= mblue;
end
end
endmodule
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