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--
-- Title       : kp_lcd
-- Design      : key_board_an
-- Author      : renuka
-- Company     : barc
--
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--
-- File        : kp_lcd.vhd
-- Generated   : Thu Dec 29 14:29:56 2005
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {kp_lcd} architecture {struct}}

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;


entity kp_lcd is
	port(
		sys_clk 		: 	in STD_LOGIC;
		sys_rst			: 	in STD_LOGIC;
--		SR 				: 	in STD_LOGIC_VECTOR(3 downto 0);
-- LCD INterface signal   .................................
		data_out 		: 	out STD_LOGIC_VECTOR(7 downto 0);
		en 				: 	out STD_LOGIC;
		r_s 			: 	out STD_LOGIC;
		r_w 			: 	out STD_LOGIC;

-- KeyBoard interface..........................................
		SC 				: 	in STD_LOGIC_VECTOR(3 downto 0);
		row_ip 			: 	out STD_LOGIC_VECTOR(3 downto 0);
		dout 			: 	out std_logic_vector(7 downto 0);
		dout_rdy 		: 	out std_logic;
		tx_busy 		:   in std_logic

		);
end kp_lcd;

--}} End of automatically maintained section

architecture struct of kp_lcd is	   	  
	component kb3 is
	generic(
		ctr5 : std_logic_vector(15 downto 0):= (others => '0');
		ctr20 : std_logic_vector(19 downto 0):= (others => '0')
	);
	port(
		sys_clk : in STD_LOGIC;
		sys_rst : in STD_LOGIC;
		SC : in  STD_LOGIC_VECTOR(3 downto 0);
		code_rdy : out STD_LOGIC;
		row_ip : out STD_LOGIC_VECTOR(3 downto 0);
		code_op : out STD_LOGIC_VECTOR(7 downto 0);
		cdout : out std_logic;
		fout : out std_logic_vector(3 downto 0)
		);
	end component;
	
	component lcd_kp_interface is
	generic(
		ctr2sec : std_logic_vector(23 downto 0):= (others => '0');
		ctr200 : std_logic_vector(11 downto 0):= (others => '0');
		ctr100 : std_logic_vector(11 downto 0):= (others => '0')
	);
	port(
		sys_clk : in STD_LOGIC;
		sys_rst : in STD_LOGIC;
		
		code : in STD_LOGIC_VECTOR(7 downto 0);
		code_rdy : in STD_LOGIC;
		
		clear : out STD_LOGIC;	
		delete : out std_logic;
		line_feed : out std_logic;
		send : out std_logic;
		lcd_data : out STD_LOGIC_VECTOR(7 downto 0);
		lcd_data_rdy : out STD_LOGIC;
		
		lcd_addr : out STD_LOGIC_VECTOR(7 downto 0);
		lcd_addr_rdy : out STD_LOGIC; 
		
		auth_word : in std_logic;
		
		addr_inc : out std_logic;
		addr_dec : out std_logic;


		Key : out std_logic_vector(15 downto 0)
		);
	end component;
	
	component lcd is
		generic(
			clk_ctr : std_logic_vector(11 downto 0):="000000000000"
		);
		Port ( 
			sys_clk : in std_logic;
			sys_rst : in std_logic;
			
			data_lcd : in std_logic_vector(7 downto 0);	  -- data coming to display
			data_lcd_rdy : in std_logic;				  -- data ready indicator
			
			addr : in std_logic_vector(7 downto 0);
			addr_rdy : in std_logic;
			
			data_out : out std_logic_vector(7 downto 0);	 -- data to lcd
			en : out std_logic;								 -- en signal to lcd
			r_w : out std_logic;							 -- r/w select to lcd
			r_s : out std_logic;							 -- data/ instruction select to lcd
			
			clear : in std_logic;								
			line_feed : in std_logic);
	end component;

	component buff is
	 port(
		 tx_busy : in STD_LOGIC;
		 send : in STD_LOGIC;
		 cmp : in STD_LOGIC;
		 UN : in STD_LOGIC;
		 PW : in STD_LOGIC;
		 GEN : in STD_LOGIC;
		 line_feed : in STD_LOGIC;
		 delete : in STD_LOGIC;
		 clear : in STD_LOGIC;
		 addr_rdy : in STD_LOGIC;
		 data_in_rdy : in STD_LOGIC;
		 sys_rst : in STD_LOGIC;
		 sys_clk : in STD_LOGIC;
		 data_in : in STD_LOGIC_VECTOR(7 downto 0);	  --given to write buffer.
--		 n_match : out STD_LOGIC;	 not using compare
--		 match : out STD_LOGIC;
		 end_cmd : out STD_LOGIC;
		 data_out_rdy : out STD_LOGIC;
		 data_out : out STD_LOGIC_VECTOR(7 downto 0)

			-- smart card reader releted ports............................
--		 scr_data_rdy : std_logic;
--		 scr_data : std_logic_vector(7 downto 0);

--		 led : out std_logic_vector(7 downto 0)
	     );
	end component;


--	constant ctr100 : std_logic_vector(15 downto 0) := X"1D4B";
--	constant ctr200 : std_logic_vector(15 downto 0) := X"3A97";
--	constant ctr2sec : std_logic_vector(27 downto 0):= X"8f0d17f";
--	constant ctr20 : std_logic_vector(21 downto 0):= "1000100101010100001111";
--	constant ctr5 : std_logic_vector(19 downto 0):= X"5b8d7";

	constant ctr100 : std_logic_vector(11 downto 0) := X"1F3";		 -- 100 us
	constant ctr200 : std_logic_vector(11 downto 0) := X"3E7";		 -- 200 us
	constant ctr2sec : std_logic_vector(23 downto 0):= X"98967F";	 -- 2sec
	constant ctr20 : std_logic_vector(19 downto 0):= X"249ef"; -- 20 ms
	constant ctr5 : std_logic_vector(15 downto 0):= X"61a7";	-- 5 ms
	
	--signal between kp & kp_lcd_interface
	signal rst1, rst2, rst3, rst4, rst5 : std_logic;
	constant logic1 : std_logic := '1';
	constant logic0 : std_logic := '0';
	signal code : std_logic_Vector(7 downto 0);
	signal code_rdy : std_logic;
	
	signal reset_ctr : std_logic_vector(2 downto 0);
	signal rst : std_logic;
	signal row_in, testctr : std_logic_vector(3 downto 0);
	-- signal between kp lcd_interface & lcd_new1 
	signal data_lcd, addr_lcd : std_logic_vector(7 downto 0);
	signal data_lcd_rdy, addr_lcd_rdy, clear, ready, line_feed, delete, send : std_logic; 
	signal keyr : std_Logic_vector(15 downto 0);
	signal fout : std_logic_vector(3 downto 0);
	signal end_cmd : std_Logic;
	signal cdout1 : std_logic;	 
	signal rst_kb_inter : std_logic;	
	signal Auth_word : std_Logic:= '0';
	signal data_rdy_d, data_rdy_d1, data_rdy_d2, data_rdy_d3 : std_Logic;
	signal data_rdy_d4 : std_Logic;
	-- signal to LCD_MOD --
	signal re : std_Logic;
	signal ikey1 : std_logic;
	signal send1,cmp1, init : std_logic; 
	signal iRst : std_logic;
	signal iSC : std_logic_vector(3 downto 0):= "1111";
	signal addr_inc, addr_dec : std_logic;
	--signal releted to buffer
	signal PW, UN, GEN : std_logic;
	signal cmp : std_logic;
	
begin
--	PULLUP1 : PULLUP port map (iRst);
	iRst <= sys_rst;
--	PULLUP3	: PULLDOWN port map (iSC(3));
--	PULLUP2 : PULLDOWN port map (iSC(2));
--	PULLUP4 : PULLDOWN port map (iSC(1));
--	PULLUP5 : PULLDOWN port map (iSC(0));
	iSC <= SC ;
--	PULLUP6 : PULLUP port map (ikey1);
--	ikey1 <= key_ip;

	KP_inter : kb3 generic map (ctr5, ctr20)
			port map (sys_clk, irst, iSC, code_rdy, row_ip, code, cdout1, fout);
	
	Inter : lcd_kp_interface generic map (ctr2sec, ctr200,ctr100)
			port map (sys_clk, irst, code, code_rdy, clear, delete, line_feed, send, 
			data_lcd, data_lcd_rdy, addr_lcd, addr_lcd_rdy, auth_word, addr_inc, addr_dec,  keyr);
	
	LCD1 : lcd generic map (ctr200)
			port map (sys_clk, irst, data_lcd, data_rdy_d1, addr_lcd, addr_lcd_rdy, data_out,
			en, r_w, r_s, clear, line_feed);

	Buffercomp : buff port map(tx_busy, send, cmp, UN, PW, GEN, line_feed, delete, clear, addr_lcd_rdy,
			data_rdy_d1, irst, sys_clk, data_lcd, end_cmd, dout_rdy, dout);

   	cmp <= '0';
	PW <= '0';
	UN <= '0';
	GEN <= '1';
	auth_word <= '0';
--	dout <= data_lcd;
--	dout_rdy <= data_rdy_d1;
    process(sys_clk, irst) begin
    if irst = '0' then
   		data_rdy_d <= '0';
		data_rdy_d1 <= '0';
		data_rdy_d2 <= '0';
		data_rdy_d3 <= '0';
		data_rdy_d4 <= '0';
	elsif sys_clk = '1' and sys_clk'event then
		data_rdy_d <= data_lcd_rdy;
		data_rdy_d1 <= data_rdy_d;
		data_rdy_d2 <= data_rdy_d1;
		data_rdy_d3 <= data_rdy_d2;
		data_Rdy_d4 <= data_rdy_d3;
	end if;
	end process;

end struct;