library IEEE;
use IEEE.std_logic_1164.all;

entity uart_receiver is
	port
	(sysclk: in std_logic;
	Bclk: in std_logic;
	BclkX8: in std_logic;
	RxD: in std_logic;	   
	RDRF,rst_b: in std_logic;
	RDR : out std_logic_vector(7 downto 0);
	setRDRF, setOE, setFE: out std_logic
	);
end uart_receiver;

architecture uart_receiver of uart_receiver is
type statetype is (IDEL, START_DETECTED,RECEIVE_DATA);
signal state, nextstate: statetype;
signal ct1: integer range 0 to 4;
signal ct2: integer range 0 to 8;
signal RSR: std_logic_vector (7 downto 0);
signal clr1, clr2, inc1, inc2, loadRDR,shiftRSR: std_logic;
signal BclkX8_Delayed,BclkX8_rising: std_logic;	   
signal check: std_logic;

begin
	BclkX8_rising<= (not BclkX8_Delayed) and BclkX8;
	check <= '0';	  
--inc1 <= '0'; inc2 <= '0';
	receive_ctl: process(RDRF, BclkX8_rising,state,RxD,ct1,ct2)	is
	begin
	clr1 <= '0';clr2 <= '0';  inc1 <= '0'; inc2 <= '0';
--	check <= not check;
	shiftRSR <= '0';loadRDR <= '0'; setRDRF <= '0'; setOE <= '0';setFE <='0';

	case state is
		when IDEL =>
		if RxD = '1' then
			nextstate <= IDEL;
		else		 
			nextstate <= START_DETECTED;
		end if;
		
		when START_DETECTED=>
		if BclkX8_rising = '1' then
			if RxD = '1' then 
				clr1 <= '1';
				nextstate <= IDEL;
			else 
				if ct1 /= 1 then
					inc1 <= '1';
					nextstate <= START_DETECTED;
				else
					clr1 <= '1';
					nextstate <= RECEIVE_DATA;
				end if;
			end if;
		else
			nextstate <= START_DETECTED;
		end if;
		
		when RECEIVE_DATA =>
		if BclkX8_rising = '1' then
			
			if ct1 = 3 then	 
			--	clr1 <= '1';
				if ct2 = 8 then
					if RDRF = '1' then
						setOE <= '1';
					elsif RxD = '0' then
						setFE <= '1';
					else
						loadRDR <= '1';		  --used to load data into  rdr
					end if; 
						setRDRF <= '1';
						clr1 <= '1';
						clr2 <= '1';  
						nextstate <= IDEL;
				else 
					shiftRSR <= '1';
					clr1 <= '1';
					inc2 <= '1';
					nextstate <= RECEIVE_DATA;
				end if;	
			else
				nextstate <= RECEIVE_DATA;
				inc1 <= '1';   
			end if;	
		else
			nextstate <= RECEIVE_DATA;
		end if;
	end case;
	end process;
	
	receive_update : process(sysclk, rst_b)
	begin
		if rst_b = '0' then
			state <= IDEL;BclkX8_Delayed <= '0';
			ct1 <= 0;
			ct2 <= 0;
			RDR <= "01100001";
		elsif sysclk'event and sysclk = '1' then
			state <= nextstate;
			if clr1 = '1' then ct1 <= 0; end if;
			if clr2 = '1' then ct2 <= 0; end if;
			if inc1 = '1' then ct1 <= ct1 + 1;end if;
			if inc2 = '1' then ct2 <= ct2 + 1;end if;
			if shiftRSR = '1' then RSR <= RxD & RSR (7 downto 1); end if;
			if loadRDR = '1' then RDR <= RSR ; end if;
			BclkX8_Delayed <= BclkX8;
		end if;
	end process;
end uart_receiver;