# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.

# Signal Activity File Name: "G:/FPGA project/m_sequence/m_sequence.saf"
# Created On: "04/20/2009 01:01:54"
# Created By: "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version"
# This file was created by the Quartus(R) II Simulator with glitch filtering enabled.

FORMAT_VERSION 1;

DEFINE_FLAG TOGGLE_RATE_FROM_SIMULATION 0x1;
DEFINE_FLAG STATIC_PROBABILITY_FROM_SIMULATION 0x2;
DEFINE_FLAG TOGGLE_RATE_FROM_USER 0x4;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER 0x8;
DEFINE_FLAG TOGGLE_RATE_FROM_USER_DEFAULT 0x10;
DEFINE_FLAG STATIC_PROBABILITY_FROM_USER_DEFAULT 0x20;
DEFINE_FLAG TOGGLE_RATE_FROM_VECTORLESS_ESTIMATION 0x40;
DEFINE_FLAG STATIC_PROBABILITY_FROM_VECTORLESS_ESTIMATION 0x80;
DEFINE_FLAG TOGGLE_RATE_ASSUMED_ZERO 0x100;
DEFINE_FLAG TOGGLE_RATE_CLIPPED_TO_MAX 0x200;

BEGIN_OUTPUT_SIGNAL_INFO;

# Output Signal Information Line Format Description:

# <one or more spaces><partial output signal name><spaces>[<flags mask><spaces><toggle rate><spaces><static probability>]<;>

 clock 0x3 1.99e+008 0.5;
 q 0x3 0 0;
 reset 0x3 0 0;

END_OUTPUT_SIGNAL_INFO;

TOGGLE_PERCENTAGE 33.3333;

PERCENTAGE_OF_TIME_SIGNALS_IN_UNKNOWN_STATE 0;