{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 00:59:22 2009 " "Info: Processing started: Mon Apr 20 00:59:22 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off m_sequence -c m_sequence " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off m_sequence -c m_sequence" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "m_sequence EP2C20Q240C8 " "Info: Selected device EP2C20Q240C8 for design \"m_sequence\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "high junction temperature 85 " "Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Warning" "WCUT_CUT_DEFAULT_OPERATING_CONDITION" "low junction temperature 0 " "Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'." {  } {  } 0 0 "The %1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "38 Top " "Info: Previous placement does not exist for 38 of 38 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0 "" 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" {  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 4 " "Info: Pin ~ASDO~ is reserved at location 4" {  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 5 " "Info: Pin ~nCSO~ is reserved at location 5" {  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ 127 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location 127" {  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "3 3 " "Warning: No exact pin location assignment(s) for 3 pins of 3 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "q " "Info: Pin q not assigned to an exact location on the device" {  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { q } } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 2 -1 0 } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clock " "Info: Pin clock not assigned to an exact location on the device" {  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { clock } } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "reset " "Info: Pin reset not assigned to an exact location on the device" {  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { reset } } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 4 -1 0 } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clock (placed in PIN 34 (CLK2, LVDSCLK1p, Input)) " "Info: Automatically promoted node clock (placed in PIN 34 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "f:/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "f:/altera/72/quartus/bin/pin_planner.ppl" { clock } } } { "m_sequence.v" "" { Text "G:/FPGA project/m_sequence/m_sequence.v" 3 -1 0 } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}