Classic Timing Analyzer report for first
Sat Apr 04 23:17:20 2009
Quartus II Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                          ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From     ; To        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 6.449 ns    ; keyin[4] ; ledout[4] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;          ;           ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EPM240F100C5       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; Off                ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                              ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                              ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Minimum tpd to report                                          ; 0 ns               ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------+
; tpd                                                                ;
+-------+-------------------+-----------------+----------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From     ; To        ;
+-------+-------------------+-----------------+----------+-----------+
; N/A   ; None              ; 6.449 ns        ; keyin[4] ; ledout[4] ;
; N/A   ; None              ; 6.095 ns        ; keyin[7] ; ledout[7] ;
; N/A   ; None              ; 6.091 ns        ; keyin[6] ; ledout[6] ;
; N/A   ; None              ; 4.850 ns        ; keyin[3] ; ledout[3] ;
; N/A   ; None              ; 4.844 ns        ; keyin[5] ; ledout[5] ;
; N/A   ; None              ; 4.839 ns        ; keyin[1] ; ledout[1] ;
; N/A   ; None              ; 4.788 ns        ; keyin[0] ; ledout[0] ;
; N/A   ; None              ; 4.785 ns        ; keyin[2] ; ledout[2] ;
+-------+-------------------+-----------------+----------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Apr 04 23:17:19 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off first -c first
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "keyin[4]" to destination pin "ledout[4]" is 6.449 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_B5; Fanout = 1; PIN Node = 'keyin[4]'
    Info: 2: + IC(2.995 ns) + CELL(2.322 ns) = 6.449 ns; Loc. = PIN_A2; Fanout = 0; PIN Node = 'ledout[4]'
    Info: Total cell delay = 3.454 ns ( 53.56 % )
    Info: Total interconnect delay = 2.995 ns ( 46.44 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Sat Apr 04 23:17:22 2009
    Info: Elapsed time: 00:00:03