LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
  ENTITY mult4x4 IS
     PORT(X,Y:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
           Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END  mult4x4;
 ARCHITECTURE behav OF mult4x4 IS
 SIGNAL A:STD_LOGIC_VECTOR(3 DOWNTO 0);
 SIGNAL B:STD_LOGIC_VECTOR(4 DOWNTO 0);
 SIGNAL C:STD_LOGIC_VECTOR(5 DOWNTO 0);
 SIGNAL D:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
  PROCESS(X,Y)
   BEGIN
     
    IF        Y(0)='0'  THEN
                          A<="0000" ; 
    ELSIF     Y(0)='1'  THEN
                          A<=X;

    END IF;
   
     IF        Y(1)='0'  THEN 
                           B<="00000";
     ELSIF     Y(1)='1'  THEN B<=X&'0';
    
    END IF;
    
     IF        Y(2)='0'  THEN
                           C<="000000";
     
     ELSIF     Y(2)='1'  THEN 
                           C<=X&"00";
    END IF; 
    
     IF        Y(3)='0'  THEN 
                           D<="0000000";
     ELSIF     Y(3)='1'  THEN 
                           D<=X&"000";
   
    END IF;
   
     Q<=A+B+C+D;
   
     END PROCESS; 
      END behav;