Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
    Info: Processing started: Tue Apr 07 16:43:18 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info: Found 1 design units, including 1 entities, in source file top.v
    Info: Found entity 1: top
Info: Found 1 design units, including 1 entities, in source file beipin0.v
    Info: Found entity 1: beipin0
Info: Found 1 design units, including 1 entities, in source file beipin1.v
    Info: Found entity 1: beipin1
Info: Found 1 design units, including 1 entities, in source file fenpin.v
    Info: Found entity 1: fenpin
Info: Elaborating entity "top" for the top level hierarchy
Info: Elaborating entity "fenpin" for hierarchy "fenpin:c"
Info: Elaborating entity "beipin0" for hierarchy "beipin0:a"
Info: Elaborating entity "beipin1" for hierarchy "beipin1:b"
Info: Duplicate registers merged to single register
    Info: Duplicate register "fenpin:c|clk2" merged to single register "beipin0:a|d", power-up level changed
    Info: Duplicate register "beipin0:a|d" merged to single register "beipin0:a|e", power-up level changed
Info: Implemented 11 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Tue Apr 07 16:43:19 2009
    Info: Elapsed time: 00:00:01