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--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
DEFAULT_DEVICES
BEGIN
AUTO_DEVICE = EP1K100FC484-1;
AUTO_DEVICE = EP1K100FC256-1;
AUTO_DEVICE = EP1K100QC208-1;
AUTO_DEVICE = EP1K50FC484-1;
AUTO_DEVICE = EP1K50FC256-1;
AUTO_DEVICE = EP1K50QC208-1;
AUTO_DEVICE = EP1K50TC144-1;
AUTO_DEVICE = EP1K30FC256-1;
AUTO_DEVICE = EP1K30QC208-1;
AUTO_DEVICE = EP1K30TC144-1;
AUTO_DEVICE = EP1K10FC256-1;
AUTO_DEVICE = EP1K10QC208-1;
AUTO_DEVICE = EP1K10TC144-1;
AUTO_DEVICE = EP1K10TC100-1;
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;
TIMING_POINT
BEGIN
MAINTAIN_STABLE_SYNTHESIS = OFF;
CUT_ALL_CLEAR_PRESET = ON;
CUT_ALL_BIDIR = ON;
END;
IGNORED_ASSIGNMENTS
BEGIN
FIT_IGNORE_TIMING = ON;
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
IGNORE_DEVICE_ASSIGNMENTS = OFF;
IGNORE_LC_ASSIGNMENTS = OFF;
IGNORE_PIN_ASSIGNMENTS = OFF;
IGNORE_CHIP_ASSIGNMENTS = OFF;
IGNORE_TIMING_ASSIGNMENTS = OFF;
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;
GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
MAX7000B_ENABLE_VREFB = OFF;
MAX7000B_ENABLE_VREFA = OFF;
MAX7000B_VCCIO_IOBANK2 = 3.3V;
MAX7000B_VCCIO_IOBANK1 = 3.3V;
CONFIG_EPROM_PULLUP_RESISTOR = ON;
CONFIG_EPROM_USER_CODE = FFFFFFFF;
FLEX_CONFIGURATION_EPROM = AUTO;
MAX7000AE_ENABLE_JTAG = ON;
MAX7000AE_USER_CODE = FFFFFFFF;
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX6000_ENABLE_JTAG = OFF;
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
MULTIVOLT_IO = OFF;
MAX7000S_ENABLE_JTAG = ON;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
MAX7000S_USER_CODE = FFFF;
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
FLEX10K_JTAG_USER_CODE = 7F;
ENABLE_INIT_DONE_OUTPUT = OFF;
ENABLE_CHIP_WIDE_OE = OFF;
ENABLE_CHIP_WIDE_RESET = OFF;
nCEO = UNRESERVED;
CLKUSR = UNRESERVED;
ADD17 = UNRESERVED;
ADD16 = UNRESERVED;
ADD15 = UNRESERVED;
ADD14 = UNRESERVED;
ADD13 = UNRESERVED;
ADD0_TO_ADD12 = UNRESERVED;
SDOUT = RESERVED_DRIVES_OUT;
RDCLK = UNRESERVED;
RDYnBUSY = UNRESERVED;
nWS_nRS_nCS_CS = UNRESERVED;
DATA1_TO_DATA7 = UNRESERVED;
DATA0 = RESERVED_TRI_STATED;
FLEX8000_ENABLE_JTAG = OFF;
CONFIG_SCHEME = ACTIVE_SERIAL;
DISABLE_TIME_OUT = OFF;
ENABLE_DCLK_OUTPUT = OFF;
RELEASE_CLEARS = OFF;
AUTO_RESTART = OFF;
USER_CLOCK = OFF;
SECURITY_BIT = OFF;
RESERVED_PINS_PERCENT = 0;
RESERVED_LCELLS_PERCENT = 0;
END;
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
AUTO_IMPLEMENT_IN_EAB = OFF;
AUTO_OPEN_DRAIN_PINS = ON;
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
AUTO_REGISTER_PACKING = OFF;
DEVICE_FAMILY = ACEX1K;
STYLE = NORMAL;
AUTO_FAST_IO = OFF;
AUTO_GLOBAL_OE = ON;
AUTO_GLOBAL_PRESET = ON;
AUTO_GLOBAL_CLEAR = ON;
AUTO_GLOBAL_CLOCK = ON;
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
OPTIMIZE_FOR_SPEED = 5;
END;
COMPILER_PROCESSING_CONFIGURATION
BEGIN
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
FITTER_SETTINGS = NORMAL;
SMART_RECOMPILE = OFF;
GENERATE_AHDL_TDO_FILE = OFF;
RPT_FILE_USER_ASSIGNMENTS = ON;
RPT_FILE_LCELL_INTERCONNECT = ON;
RPT_FILE_HIERARCHY = ON;
RPT_FILE_EQUATIONS = ON;
LINKED_SNF_EXTRACTOR = OFF;
OPTIMIZE_TIMING_SNF = OFF;
TIMING_SNF_EXTRACTOR = ON;
FUNCTIONAL_SNF_EXTRACTOR = OFF;
DESIGN_DOCTOR_RULES = EPLD;
DESIGN_DOCTOR = OFF;
END;
COMPILER_INTERFACES_CONFIGURATION
BEGIN
VHDL_WRITER_VERSION = VHDL93;
VHDL_READER_VERSION = VHDL93;
USE_ADT_PALACE_FOR_MAX = OFF;
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
SYNOPSYS_DESIGNWARE = OFF;
SYNOPSYS_COMPILER = DESIGN;
USE_SYNOPSYS_SYNTHESIS = OFF;
VHDL_NETLIST_WRITER = OFF;
VERILOG_NETLIST_WRITER = OFF;
XNF_GENERATE_AHDL_TDX_FILE = ON;
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
EDIF_OUTPUT_VERSION = 200;
EDIF_NETLIST_WRITER = OFF;
END;
CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
MASTER_RESET = OFF;
EXPANDER_NETWORKS = ON;
RACE_CONDITIONS = ON;
DELAY_CHAINS = ON;
ASYNCHRONOUS_INPUTS = ON;
PRESET_CLEAR_NETWORKS = ON;
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
MULTI_CLOCK_NETWORKS = ON;
MULTI_LEVEL_CLOCKS = ON;
GATED_CLOCKS = ON;
RIPPLE_CLOCKS = ON;
END;
SIMULATOR_CONFIGURATION
BEGIN
BIDIR_PIN = STRONG;
END_TIME = 0.0ns;
START_TIME = 0.0ns;
GLITCH_TIME = 0.0ns;
GLITCH = OFF;
OSCILLATION_TIME = 0.0ns;
OSCILLATION = OFF;
CHECK_OUTPUTS = OFF;
SETUP_HOLD = OFF;
USE_DEVICE = OFF;
END;
TIMING_ANALYZER_CONFIGURATION
BEGIN
CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
LIST_PATH_FREQUENCY = 10MHz;
LIST_PATH_COUNT = 10;
REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
INCLUDE_PATHS_LESS_THAN = OFF;
INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
INCLUDE_PATHS_GREATER_THAN = OFF;
DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
CELL_WIDTH = 18;
LIST_ONLY_LONGEST_PATH = ON;
CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
CUT_OFF_IO_PIN_FEEDBACK = ON;
AUTO_RECALCULATE = OFF;
ANALYSIS_MODE = DELAY_MATRIX;
END;
OTHER_CONFIGURATION
BEGIN
LAST_MAXPLUS2_VERSION = 10.2;
FLEX_10K_52_COLUMNS = 40;
DEFAULT_9K_EXP_PER_LCELL = 1/2;
LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
LCELLS_PER_ROW_PERCENT = 100;
FAN_IN_PER_LCELL_PERCENT = 100;
EXP_PER_LCELL_PERCENT = 100;
ROW_PINS_PERCENT = 50;
ORIGINAL_MAXPLUS2_VERSION = 10.2;
COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
EXPLICIT_FAMILY = OFF;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = ON;
REFACTORIZATION = ON;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = ON;
TURBO_BIT = ON;
XOR_SYNTHESIS = ON;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = ON;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = ON;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = ON;
REDUCE_LOGIC = ON;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = FULL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = AUTO;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = AUTO;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = ON;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = ON;
SOFT_BUFFER_INSERTION = OFF;
FAST_IO = OFF;
IGNORE_SOFT_BUFFERS = OFF;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = ON;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = -1;
CARRY_CHAIN = IGNORE;
CASCADE_CHAIN_LENGTH = -1;
CASCADE_CHAIN = IGNORE;
END;
DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
REGISTER_OPTIMIZATION = OFF;
USE_LPM_FOR_AHDL_OPERATORS = OFF;
RESYNTHESIZE_NETWORK = OFF;
MULTI_LEVEL_FACTORING = OFF;
SUBFACTOR_EXTRACTION = OFF;
REFACTORIZATION = OFF;
NOT_GATE_PUSH_BACK = ON;
DUPLICATE_LOGIC_EXTRACTION = OFF;
REDUCE_LOGIC = OFF;
DECOMPOSE_GATES = OFF;
SOFT_BUFFER_INSERTION = ON;
IGNORE_SOFT_BUFFERS = ON;
PARALLEL_EXPANDERS = OFF;
TURBO_BIT = OFF;
XOR_SYNTHESIS = OFF;
SLOW_SLEW_RATE = OFF;
MINIMIZATION = PARTIAL;
CARRY_CHAIN_LENGTH = 32;
CARRY_CHAIN = MANUAL;
CASCADE_CHAIN_LENGTH = 2;
CASCADE_CHAIN = MANUAL;
END;
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