// -------------------------------------------------------------------------//Syndrome generator circuit in Reed-Solomon Decoder//Copyright (C) Tue Apr  2 17:07:53 2002//by Ming-Han Lei(hendrik@humanistic.org)////This program is free software; you can redistribute it and/or//modify it under the terms of the GNU Lesser General Public License//as published by the Free Software Foundation; either version 2//of the License, or (at your option) any later version.////This program is distributed in the hope that it will be useful,//but WITHOUT ANY WARRANTY; without even the implied warranty of//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the//GNU General Public License for more details.////You should have received a copy of the GNU Lesser General Public License//along with this program; if not, write to the Free Software//Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.// --------------------------------------------------------------------------module rsdec_syn_m0 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[7];		y[1] = x[0] ^ x[7];		y[2] = x[1] ^ x[7];		y[3] = x[2];		y[4] = x[3];		y[5] = x[4];		y[6] = x[5];		y[7] = x[6] ^ x[7];	endendmodulemodule rsdec_syn_m1 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[6] ^ x[7];		y[1] = x[6];		y[2] = x[0] ^ x[6];		y[3] = x[1] ^ x[7];		y[4] = x[2];		y[5] = x[3];		y[6] = x[4];		y[7] = x[5] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m2 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[5] ^ x[6] ^ x[7];		y[1] = x[5];		y[2] = x[5] ^ x[7];		y[3] = x[0] ^ x[6];		y[4] = x[1] ^ x[7];		y[5] = x[2];		y[6] = x[3];		y[7] = x[4] ^ x[5] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m3 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[4] ^ x[5] ^ x[6] ^ x[7];		y[1] = x[4];		y[2] = x[4] ^ x[6] ^ x[7];		y[3] = x[5] ^ x[7];		y[4] = x[0] ^ x[6];		y[5] = x[1] ^ x[7];		y[6] = x[2];		y[7] = x[3] ^ x[4] ^ x[5] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m4 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[3] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[1] = x[3];		y[2] = x[3] ^ x[5] ^ x[6] ^ x[7];		y[3] = x[4] ^ x[6] ^ x[7];		y[4] = x[5] ^ x[7];		y[5] = x[0] ^ x[6];		y[6] = x[1] ^ x[7];		y[7] = x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m5 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[1] = x[2];		y[2] = x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[3] = x[3] ^ x[5] ^ x[6] ^ x[7];		y[4] = x[4] ^ x[6] ^ x[7];		y[5] = x[5] ^ x[7];		y[6] = x[0] ^ x[6];		y[7] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[6];	endendmodulemodule rsdec_syn_m6 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[1] = x[1] ^ x[7];		y[2] = x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[3] = x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[4] = x[3] ^ x[5] ^ x[6] ^ x[7];		y[5] = x[4] ^ x[6] ^ x[7];		y[6] = x[5] ^ x[7];		y[7] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[5];	endendmodulemodule rsdec_syn_m7 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[5];		y[1] = x[0] ^ x[6];		y[2] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[3] = x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[4] = x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[5] = x[3] ^ x[5] ^ x[6] ^ x[7];		y[6] = x[4] ^ x[6] ^ x[7];		y[7] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[7];	endendmodulemodule rsdec_syn_m8 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[7];		y[1] = x[5] ^ x[7];		y[2] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[3] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[4] = x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[5] = x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[6] = x[3] ^ x[5] ^ x[6] ^ x[7];		y[7] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[6];	endendmodulemodule rsdec_syn_m9 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[6];		y[1] = x[4] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[3] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[4] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[5] = x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[6] = x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[7] = x[0] ^ x[1] ^ x[2] ^ x[5] ^ x[7];	endendmodulemodule rsdec_syn_m10 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[1] ^ x[2] ^ x[5] ^ x[7];		y[1] = x[3] ^ x[5] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6];		y[3] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[4] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[5] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[6] = x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[7] = x[0] ^ x[1] ^ x[4] ^ x[6];	endendmodulemodule rsdec_syn_m11 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[1] ^ x[4] ^ x[6];		y[1] = x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[3] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6];		y[4] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[5] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[6] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[7] = x[0] ^ x[3] ^ x[5];	endendmodulemodule rsdec_syn_m12 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[3] ^ x[5];		y[1] = x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[2] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[3] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[4] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6];		y[5] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[6] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[7] = x[2] ^ x[4] ^ x[7];	endendmodulemodule rsdec_syn_m13 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[2] ^ x[4] ^ x[7];		y[1] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[2] = x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[3] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[4] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[5] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6];		y[6] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[7] = x[1] ^ x[3] ^ x[6];	endendmodulemodule rsdec_syn_m14 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[1] ^ x[3] ^ x[6];		y[1] = x[1] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[3] = x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[4] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[5] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[6] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6];		y[7] = x[0] ^ x[2] ^ x[5] ^ x[7];	endendmodulemodule rsdec_syn_m15 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[2] ^ x[5] ^ x[7];		y[1] = x[0] ^ x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[3] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[4] = x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[5] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[6] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[7] = x[1] ^ x[4] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m16 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[1] ^ x[4] ^ x[6] ^ x[7];		y[1] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6];		y[2] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5];		y[3] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[4] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[5] = x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[6] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[7] = x[0] ^ x[3] ^ x[5] ^ x[6];	endendmodulemodule rsdec_syn_m17 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[3] ^ x[5] ^ x[6];		y[1] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[7];		y[2] = x[1] ^ x[2] ^ x[3] ^ x[4];		y[3] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5];		y[4] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[5] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[6] = x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[7] = x[2] ^ x[4] ^ x[5] ^ x[7];	endendmodulemodule rsdec_syn_m18 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[2] ^ x[4] ^ x[5] ^ x[7];		y[1] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[2] ^ x[3];		y[3] = x[1] ^ x[2] ^ x[3] ^ x[4];		y[4] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5];		y[5] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[6] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[7] = x[1] ^ x[3] ^ x[4] ^ x[6];	endendmodulemodule rsdec_syn_m19 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[1] ^ x[3] ^ x[4] ^ x[6];		y[1] = x[1] ^ x[2] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[2] ^ x[7];		y[3] = x[0] ^ x[1] ^ x[2] ^ x[3];		y[4] = x[1] ^ x[2] ^ x[3] ^ x[4];		y[5] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5];		y[6] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[7] = x[0] ^ x[2] ^ x[3] ^ x[5] ^ x[7];	endendmodulemodule rsdec_syn_m20 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[2] ^ x[3] ^ x[5] ^ x[7];		y[1] = x[0] ^ x[1] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[2] = x[0] ^ x[1] ^ x[6];		y[3] = x[0] ^ x[1] ^ x[2] ^ x[7];		y[4] = x[0] ^ x[1] ^ x[2] ^ x[3];		y[5] = x[1] ^ x[2] ^ x[3] ^ x[4];		y[6] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5];		y[7] = x[1] ^ x[2] ^ x[4] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m21 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[1] ^ x[2] ^ x[4] ^ x[6] ^ x[7];		y[1] = x[0] ^ x[1] ^ x[3] ^ x[4] ^ x[5] ^ x[6];		y[2] = x[0] ^ x[5];		y[3] = x[0] ^ x[1] ^ x[6];		y[4] = x[0] ^ x[1] ^ x[2] ^ x[7];		y[5] = x[0] ^ x[1] ^ x[2] ^ x[3];		y[6] = x[1] ^ x[2] ^ x[3] ^ x[4];		y[7] = x[0] ^ x[1] ^ x[3] ^ x[5] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m22 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[1] ^ x[3] ^ x[5] ^ x[6] ^ x[7];		y[1] = x[0] ^ x[2] ^ x[3] ^ x[4] ^ x[5];		y[2] = x[4] ^ x[7];		y[3] = x[0] ^ x[5];		y[4] = x[0] ^ x[1] ^ x[6];		y[5] = x[0] ^ x[1] ^ x[2] ^ x[7];		y[6] = x[0] ^ x[1] ^ x[2] ^ x[3];		y[7] = x[0] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];	endendmodulemodule rsdec_syn_m23 (y, x);	input [7:0] x;	output [7:0] y;	reg [7:0] y;	always @ (x)	begin		y[0] = x[0] ^ x[2] ^ x[4] ^ x[5] ^ x[6] ^ x[7];		y[1] = x[1] ^ x[2] ^ x[3] ^ x[4];		y[2] = x[3] ^ x[6] ^ x[7];		y[3] = x[4] ^ x[7];		y[4] = x[0] ^ x[5];