# Xilinx CORE Generator 6.1iSELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0CSET primitive_selection = Optimize_For_AreaCSET init_value = 0CSET register_inputs = falseCSET write_enable_polarity = Active_HighCSET init_pin = falseCSET initialization_pin_polarity = Active_HighCSET global_init_value = 0CSET select_primitive = 16kx1CSET enable_pin = falseCSET write_mode = Read_After_WriteCSET port_configuration = Read_And_WriteCSET component_name = buffer_imgCSET active_clock_edge = Rising_Edge_TriggeredCSET handshaking_pins = falseCSET width = 8CSET load_init_file = trueCSET enable_pin_polarity = Active_HighCSET additional_output_pipe_stages = 0CSET coefficient_file = E:\VHDL\PFCarrera\FPGA\Coregen\buffer_img.coeCSET has_limit_data_pitch = falseCSET limit_data_pitch = 18CSET depth = 51200GENERATE