# Xilinx CORE Generator 6.1i# Username = Administrador# COREGenPath = C:\Winapp\Xilinx\coregen# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen# OverwriteFiles = True# Core name: buffer_comp# Number of Primitives in design: 37# Number of CLBs used in design cannot be determined when there is no RPMed logic# Number of Slices used in design cannot be determined when there is no RPMed logic# Number of LUT sites used in design: 21# Number of LUTs used in design: 21# Number of REG used in design: 2# Number of SRL16s used in design: 0# Number of Distributed RAM primitives used in design: 0# Number of Block Memories used in design: 5# Number of Dedicated Multipliers used in design: 0# Number of HU_SETs used: 0# SET BusFormat = BusFormatAngleBracketNotRippedSET SimulationOutputProducts = VHDLSET XilinxFamily = Virtex2SET OutputOption = DesignFlowSET DesignFlow = VHDLSET FlowVendor = OtherSET FormalVerification = NoneSELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0CSET primitive_selection = Optimize_For_AreaCSET init_value = 0CSET register_inputs = falseCSET write_enable_polarity = Active_HighCSET init_pin = falseCSET initialization_pin_polarity = Active_HighCSET global_init_value = 0CSET select_primitive = 16kx1CSET enable_pin = falseCSET write_mode = Read_Before_WriteCSET port_configuration = Read_And_WriteCSET component_name = buffer_compCSET active_clock_edge = Rising_Edge_TriggeredCSET handshaking_pins = falseCSET width = 12CSET load_init_file = falseCSET enable_pin_polarity = Active_HighCSET additional_output_pipe_stages = 0CSET has_limit_data_pitch = falseCSET limit_data_pitch = 18CSET depth = 5632GENERATE