(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))(status (written (timeStamp 2004 10 12 17 28 41)   (author "Xilinx, Inc.")   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.1i"))))   (comment "                                                                                      This file is owned and controlled by Xilinx and must be used                    solely for design, simulation, implementation and creation of                   design files limited to Xilinx devices or technologies. Use                     with non-Xilinx devices or technologies is expressly prohibited                 and immediately terminates your license.                                                                                                                        XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'                   SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                         XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION                 AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION                     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                       IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                         AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE                FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                        WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                         IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR                  REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF                 INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS                 FOR A PARTICULAR PURPOSE.                                                                                                                                       Xilinx products are not intended for use in life support                        appliances, devices, or systems. Use in such applications are                   expressly prohibited.                                                                                                                                           (c) Copyright 1995-2003 Xilinx, Inc.                                            All rights reserved.                                                                                                                                         ")   (comment "Core parameters: ")       (comment "c_sinit_value = 0 ")       (comment "c_has_en = 0 ")       (comment "c_reg_inputs = 0 ")       (comment "c_yclk_is_rising = 1 ")       (comment "c_ysinit_is_high = 1 ")       (comment "c_ywe_is_high = 1 ")       (comment "c_yprimitive_type = 16kx1 ")       (comment "c_ytop_addr = 1024 ")       (comment "c_yhierarchy = hierarchy1 ")       (comment "c_has_limit_data_pitch = 0 ")       (comment "c_has_rdy = 0 ")       (comment "c_write_mode = 0 ")       (comment "c_width = 20 ")       (comment "c_yuse_single_primitive = 0 ")       (comment "c_has_nd = 0 ")       (comment "c_has_we = 0 ")       (comment "c_enable_rlocs = 0 ")       (comment "c_has_rfd = 0 ")       (comment "c_has_din = 0 ")       (comment "c_ybottom_addr = 0 ")       (comment "c_pipe_stages = 0 ")       (comment "c_yen_is_high = 1 ")       (comment "c_family = virtex2 ")       (comment "InstanceName = huff_rom ")       (comment "c_depth = 352 ")       (comment "c_has_default_data = 0 ")       (comment "c_limit_data_pitch = 18 ")       (comment "c_has_sinit = 0 ")       (comment "c_mem_init_file = huff_rom.mif ")       (comment "c_default_data = 0 ")       (comment "c_ymake_bmm = 0 ")       (comment "c_addr_width = 9 ")   (external xilinxun (edifLevel 0)      (technology (numberDefinition))       (cell VCC (cellType GENERIC)           (view view_1 (viewType NETLIST)               (interface                   (port P (direction OUTPUT))               )           )       )       (cell GND (cellType GENERIC)           (view view_1 (viewType NETLIST)               (interface                   (port G (direction OUTPUT))               )           )       )       (cell RAMB16_S36 (cellType GENERIC)           (view view_1 (viewType NETLIST)               (interface                   (port WE (direction INPUT))                   (port EN (direction INPUT))                   (port SSR (direction INPUT))                   (port CLK (direction INPUT))                   (port (rename DI_0_ "DI<0>") (direction INPUT))                   (port (rename DI_1_ "DI<1>") (direction INPUT))                   (port (rename DI_2_ "DI<2>") (direction INPUT))                   (port (rename DI_3_ "DI<3>") (direction INPUT))                   (port (rename DI_4_ "DI<4>") (direction INPUT))                   (port (rename DI_5_ "DI<5>") (direction INPUT))                   (port (rename DI_6_ "DI<6>") (direction INPUT))                   (port (rename DI_7_ "DI<7>") (direction INPUT))                   (port (rename DI_8_ "DI<8>") (direction INPUT))                   (port (rename DI_9_ "DI<9>") (direction INPUT))                   (port (rename DI_10_ "DI<10>") (direction INPUT))                   (port (rename DI_11_ "DI<11>") (direction INPUT))                   (port (rename DI_12_ "DI<12>") (direction INPUT))                   (port (rename DI_13_ "DI<13>") (direction INPUT))                   (port (rename DI_14_ "DI<14>") (direction INPUT))                   (port (rename DI_15_ "DI<15>") (direction INPUT))                   (port (rename DI_16_ "DI<16>") (direction INPUT))                   (port (rename DI_17_ "DI<17>") (direction INPUT))                   (port (rename DI_18_ "DI<18>") (direction INPUT))                   (port (rename DI_19_ "DI<19>") (direction INPUT))                   (port (rename DI_20_ "DI<20>") (direction INPUT))                   (port (rename DI_21_ "DI<21>") (direction INPUT))                   (port (rename DI_22_ "DI<22>") (direction INPUT))                   (port (rename DI_23_ "DI<23>") (direction INPUT))                   (port (rename DI_24_ "DI<24>") (direction INPUT))                   (port (rename DI_25_ "DI<25>") (direction INPUT))                   (port (rename DI_26_ "DI<26>") (direction INPUT))                   (port (rename DI_27_ "DI<27>") (direction INPUT))                   (port (rename DI_28_ "DI<28>") (direction INPUT))                   (port (rename DI_29_ "DI<29>") (direction INPUT))                   (port (rename DI_30_ "DI<30>") (direction INPUT))                   (port (rename DI_31_ "DI<31>") (direction INPUT))                   (port (rename DO_0_ "DO<0>") (direction OUTPUT))                   (port (rename DO_1_ "DO<1>") (direction OUTPUT))                   (port (rename DO_2_ "DO<2>") (direction OUTPUT))                   (port (rename DO_3_ "DO<3>") (direction OUTPUT))                   (port (rename DO_4_ "DO<4>") (direction OUTPUT))                   (port (rename DO_5_ "DO<5>") (direction OUTPUT))                   (port (rename DO_6_ "DO<6>") (direction OUTPUT))                   (port (rename DO_7_ "DO<7>") (direction OUTPUT))                   (port (rename DO_8_ "DO<8>") (direction OUTPUT))                   (port (rename DO_9_ "DO<9>") (direction OUTPUT))                   (port (rename DO_10_ "DO<10>") (direction OUTPUT))                   (port (rename DO_11_ "DO<11>") (direction OUTPUT))                   (port (rename DO_12_ "DO<12>") (direction OUTPUT))                   (port (rename DO_13_ "DO<13>") (direction OUTPUT))                   (port (rename DO_14_ "DO<14>") (direction OUTPUT))                   (port (rename DO_15_ "DO<15>") (direction OUTPUT))                   (port (rename DO_16_ "DO<16>") (direction OUTPUT))                   (port (rename DO_17_ "DO<17>") (direction OUTPUT))                   (port (rename DO_18_ "DO<18>") (direction OUTPUT))                   (port (rename DO_19_ "DO<19>") (direction OUTPUT))                   (port (rename DO_20_ "DO<20>") (direction OUTPUT))                   (port (rename DO_21_ "DO<21>") (direction OUTPUT))                   (port (rename DO_22_ "DO<22>") (direction OUTPUT))                   (port (rename DO_23_ "DO<23>") (direction OUTPUT))                   (port (rename DO_24_ "DO<24>") (direction OUTPUT))                   (port (rename DO_25_ "DO<25>") (direction OUTPUT))                   (port (rename DO_26_ "DO<26>") (direction OUTPUT))                   (port (rename DO_27_ "DO<27>") (direction OUTPUT))                   (port (rename DO_28_ "DO<28>") (direction OUTPUT))                   (port (rename DO_29_ "DO<29>") (direction OUTPUT))                   (port (rename DO_30_ "DO<30>") (direction OUTPUT))                   (port (rename DO_31_ "DO<31>") (direction OUTPUT))                   (port (rename ADDR_0_ "ADDR<0>") (direction INPUT))                   (port (rename ADDR_1_ "ADDR<1>") (direction INPUT))                   (port (rename ADDR_2_ "ADDR<2>") (direction INPUT))                   (port (rename ADDR_3_ "ADDR<3>") (direction INPUT))                   (port (rename ADDR_4_ "ADDR<4>") (direction INPUT))                   (port (rename ADDR_5_ "ADDR<5>") (direction INPUT))                   (port (rename ADDR_6_ "ADDR<6>") (direction INPUT))                   (port (rename ADDR_7_ "ADDR<7>") (direction INPUT))                   (port (rename ADDR_8_ "ADDR<8>") (direction INPUT))                   (port (rename DIP_0_ "DIP<0>") (direction INPUT))                   (port (rename DIP_1_ "DIP<1>") (direction INPUT))                   (port (rename DIP_2_ "DIP<2>") (direction INPUT))                   (port (rename DIP_3_ "DIP<3>") (direction INPUT))                   (port (rename DOP_0_ "DOP<0>") (direction OUTPUT))                   (port (rename DOP_1_ "DOP<1>") (direction OUTPUT))                   (port (rename DOP_2_ "DOP<2>") (direction OUTPUT))                   (port (rename DOP_3_ "DOP<3>") (direction OUTPUT))               )           )       )   )(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))(cell huff_rom (cellType GENERIC) (view view_1 (viewType NETLIST)  (interface   (port ( array ( rename addr "addr<8:0>") 9 ) (direction INPUT))   (port ( rename clk "clk") (direction INPUT))   (port ( array ( rename dout "dout<19:0>") 20 ) (direction OUTPUT))   )  (contents   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))   (instance B5      (viewRef view_1 (cellRef RAMB16_S36 (libraryRef xilinxun)))      (property INIT_00 (string "000700f8000600780004001a0003000b0002000400010001000100000003000a"))      (property INIT_01 (string "000801f6000600790004001b0003000c00000000000fff83000fff82000903f6"))      (property INIT_02 (string "0004001c00000000000fff88000fff87000fff86000fff85000fff84000a07f6"))      (property INIT_03 (string "000fff8d000fff8c000fff8b000fff8a000fff89000b0ff4000903f7000700f9"))      (property INIT_04 (string "000fff91000fff90000fff8f000b0ff5000801f70005003a00000000000fff8e"))      (property INIT_05 (string "000fff96000903f80005003b00000000000fff95000fff94000fff93000fff92"))      (property INIT_06 (string "00000000000fff9d000fff9c000fff9b000fff9a000fff99000fff98000fff97"))      (property INIT_07 (string "000fffa3000fffa2000fffa1000fffa0000fff9f000fff9e000a07f70006007a"))      (property INIT_08 (string "000fffa8000fffa7000fffa6000b0ff60006007b00000000000fffa5000fffa4"))      (property INIT_09 (string "000b0ff7000700fa00000000000fffad000fffac000fffab000fffaa000fffa9"))      (property INIT_0A (string "000fffb5000fffb4000fffb3000fffb2000fffb1000fffb0000fffaf000fffae"))      (property INIT_0B (string "000fffba000fffb9000fffb8000fffb7000fffb6000e7fc0000801f800000000"))      (property INIT_0C (string "000fffc0000fffbf000fffbe000801f900000000000fffbd000fffbc000fffbb"))      (property INIT_0D (string "000801fa00000000000fffc6000fffc5000fffc4000fffc3000fffc2000fffc1"))      (property INIT_0E (string "000fffce000fffcd000fffcc000fffcb000fffca000fffc9000fffc8000fffc7"))      (property INIT_0F (string "000fffd4000fffd3000fffd2000fffd1000fffd0000903f900000000000fffcf"))      (property INIT_10 (string "000fffda000fffd9000903fa00000000000fffd8000fffd7000fffd6000fffd5"))      (property INIT_11 (string "00000000000fffe1000fffe0000fffdf000fffde000fffdd000fffdc000fffdb"))      (property INIT_12 (string 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"00000000000fff9e000fff9d000fff9c000fff9b000fff9a000fff99000fff98"))      (property INIT_1D (string "000fffa4000fffa3000fffa2000fffa1000fffa0000fff9f000903f90005003b"))      (property INIT_1E (string "000fffa9000fffa8000fffa7000a07f70006007900000000000fffa6000fffa5"))      (property INIT_1F (string "000a07f80006007a00000000000fffae000fffad000fffac000fffab000fffaa"))      (property INIT_20 (string "000fffb6000fffb5000fffb4000fffb3000fffb2000fffb1000fffb0000fffaf"))      (property INIT_21 (string "000fffbc000fffbb000fffba000fffb9000fffb8000fffb7000700f900000000"))      (property INIT_22 (string "000fffc2000fffc1000fffc0000801f700000000000fffbf000fffbe000fffbd"))      (property INIT_23 (string "000801f800000000000fffc8000fffc7000fffc6000fffc5000fffc4000fffc3"))      (property INIT_24 (string "000fffd0000fffcf000fffce000fffcd000fffcc000fffcb000fffca000fffc9"))      (property INIT_25 (string "000fffd6000fffd5000fffd4000fffd3000fffd2000801f900000000000fffd1"))      (property INIT_26 (string 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