----------------------------------------------------------------------------------     This file is owned and controlled by Xilinx and must be used           ----     solely for design, simulation, implementation and creation of          ----     design files limited to Xilinx devices or technologies. Use            ----     with non-Xilinx devices or technologies is expressly prohibited        ----     and immediately terminates your license.                               ----                                                                            ----     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          ----     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                ----     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        ----     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            ----     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              ----     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                ----     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       ----     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               ----     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                ----     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         ----     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        ----     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        ----     FOR A PARTICULAR PURPOSE.                                              ----                                                                            ----     Xilinx products are not intended for use in life support               ----     appliances, devices, or systems. Use in such applications are          ----     expressly prohibited.                                                  ----                                                                            ----     (c) Copyright 1995-2003 Xilinx, Inc.                                   ----     All rights reserved.                                                   ------------------------------------------------------------------------------------ The following code must appear in the VHDL architecture header:------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAGcomponent buffer_comp	port (	addr: IN std_logic_VECTOR(12 downto 0);	clk: IN std_logic;	din: IN std_logic_VECTOR(11 downto 0);	dout: OUT std_logic_VECTOR(11 downto 0);	we: IN std_logic);end component;-- COMP_TAG_END ------ End COMPONENT Declaration -------------- The following code must appear in the VHDL architecture-- body. Substitute your own instance name and net names.------------- Begin Cut here for INSTANTIATION Template ----- INST_TAGyour_instance_name : buffer_comp		port map (			addr => addr,			clk => clk,			din => din,			dout => dout,			we => we);-- INST_TAG_END ------ End INSTANTIATION Template -------------- You must compile the wrapper file buffer_comp.vhd when simulating-- the core, buffer_comp. When compiling the wrapper file, be sure to-- reference the XilinxCoreLib VHDL simulation library. For detailed-- instructions, please refer to the "CORE Generator Guide".