# Xilinx CORE Generator 6.1i# Username = Administrador# COREGenPath = C:\Winapp\Xilinx\coregen# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen# OverwriteFiles = True# Core name: DA_2D_DCT# Number of Primitives in design: 9075# Number of CLBs used in design cannot be determined when there is no RPMed logic# Number of Slices used in design cannot be determined when there is no RPMed logic# Number of LUT sites used in design: 3021# Number of LUTs used in design: 2969# Number of REG used in design: 3452# Number of SRL16s used in design: 52# Number of Distributed RAM primitives used in design: 0# Number of Block Memories used in design: 1# Number of Dedicated Multipliers used in design: 0# Number of HU_SETs used: 0# SET BusFormat = BusFormatAngleBracketNotRippedSET SimulationOutputProducts = VHDLSET XilinxFamily = Virtex2SET OutputOption = DesignFlowSET DesignFlow = VHDLSET FlowVendor = OtherSET FormalVerification = NoneSELECT 2-D_Discrete_Cosine_Transform Virtex2 Xilinx,_Inc. 2.0CSET input_data_width = 8CSET precision_control = RoundCSET result_width = 19CSET enable_symmetry = trueCSET operation = Forward_DCTCSET internal_width = 19CSET input_data_type = SignedCSET coefficient_width = 24CSET has_reset = falseCSET component_name = dct2dCSET transpose_memory = BlockCSET clock_cycles_per_input_sample = 9GENERATE