# Reading C:/Libero/Model/tcl/vsim/pref.tcl 
# do run.do 
# Modifying modelsim.ini
# Modifying modelsim.ini
# Model Technology ModelSim ACTEL vcom 6.3c Compiler 2007.09 Sep 12 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity a_4_bit_comparator
# -- Compiling architecture arch of a_4_bit_comparator
# Model Technology ModelSim ACTEL vcom 6.3c Compiler 2007.09 Sep 12 2007
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package math_real
# -- Loading package numeric_bit
# -- Loading package tbdefinitions
# -- Loading package std_logic_unsigned
# -- Compiling entity stimulus
# -- Compiling architecture stimulator of stimulus
# -- Loading entity tb_clock_minmax
# -- Compiling entity testbench
# -- Compiling architecture tbgeneratedcode of testbench
# -- Loading entity stimulus
# -- Loading entity a_4_bit_comparator
# vsim -L proasic3 -L presynth -t 1ps presynth.testbench 
# //  ModelSim ACTEL 6.3c Sep 12 2007 
# //
# //  Copyright 1991-2007 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.std_logic_textio(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.math_real(body)
# Loading ieee.numeric_bit(body)
# Loading syncad_vhdl_lib.tbdefinitions(body)
# Loading ieee.std_logic_unsigned(body)
# Loading presynth.testbench(tbgeneratedcode)
# Loading presynth.stimulus(stimulator)
# Loading syncad_vhdl_lib.tb_clock_minmax(behavioral)
# Loading presynth.a_4_bit_comparator(arch)