// key_control.v
module key_control(clk_48M,up,up_done,down,down_done);
input clk_48M;
input up;
output up_done;
reg upout1,upout2,upout3;

input down;
output down_done;
reg downout1,downout2,downout3;


reg[15:0]clkdiv;

always@(posedge clk_48M)
begin
clkdiv<=clkdiv+1'b1;
end

assign up_done=upout1&upout2&upout3;

always@(posedge clkdiv[15])
begin
upout1<=up;
upout2<=upout1;
upout3<=upout2;
end


assign down_done=downout1&downout2&downout3;

always@(posedge clkdiv[15])
begin
downout1<=down;
downout2<=downout1;
downout3<=downout2;
end

endmodule