// key_top.v
module key(clk_48M,up,led,down,en);
input clk_48M;
input up,down,en;
output[7:0] led;
reg[2:0] cnt1=3'b111,cnt=3'b000;
reg[7:0] led0,led1;
reg en_buf=1'b1;
key_control  u1(
               .clk_48M(clk_48M),
               .up(up),
               .up_done(up_done),
               .down(down),
               .down_done(down_done)
                          );
always@(posedge en)
begin
en_buf<=~en_buf;
end

assign led=en_buf?led0:led1;

always@(posedge up_done) 
 begin
       cnt<=cnt+1'b1;
        case(cnt)
         	3'b000: led0 <= 8'b11111110;
			3'b001: led0 <= 8'b11111101;
			3'b010: led0 <= 8'b11111011;
			3'b011: led0 <= 8'b11110111;
			3'b100: led0 <= 8'b11101111;
			3'b101: led0 <= 8'b11011111;
			3'b110: led0 <= 8'b10111111;
			default: led0 <= 8'b01111111;
         endcase
 end
always@(posedge down_done)
  begin
      cnt1<=cnt1-1'b1;
      case(cnt1)
         	3'b000: led1 <= 8'b11111110;
			3'b001: led1 <= 8'b11111101;
			3'b010: led1<= 8'b11111011;
			3'b011: led1 <= 8'b11110111;
			3'b100: led1 <= 8'b11101111;
			3'b101: led1 <= 8'b11011111;
			3'b110: led1 <= 8'b10111111;
			default: led1 <= 8'b01111111;
      endcase
  end
endmodule